### Abstract

This paper presents an algorithm for the estimation of power in static CMOS digital circuits using a stochastic approach. The salient feature of this approach is that it can be used to estimate the power of reasonably large digital circuits in a very short time, due to its hierarchical nature. Here, the given circuit is first partitioned into smaller sub-circuits. Then, the sub-circuits are modeled using state transition diagrams (stds), and the steady-state probabilities associated with the various states are computed by treating them as irreducible Markov chains. Finally, the energy associated with each sub-circuit is computed, and the total energy of the circuit is obtained by summing up the energies of its constituent sub-circuits. In the proposed hierarchical approach, the energies associated with various edges in a sub-circuit are calculated only once using SPICE and these values are used several times; this results in large savings in computation time. Another advantage of the proposed approach is that we can accommodate switching activities at the transistor level and not necessarily at gate or higher levels. Experimental results show that the estimated power is in close agreement with the actual power obtained from exhaustive SPICE simulations, but the computation time required by the proposed approach is orders of magnitude less than that of SPICE.

Original language | English (US) |
---|---|

Pages (from-to) | 9-14 |

Number of pages | 6 |

Journal | Proceedings - Design Automation Conference |

State | Published - Jan 1 1996 |

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### Cite this

*Proceedings - Design Automation Conference*, 9-14.

**HEAT : Hierarchical Energy Analysis Tool.** / Satyanarayana, Janardhan H.; Parhi, Keshab K.

Research output: Contribution to journal › Article

*Proceedings - Design Automation Conference*, pp. 9-14.

}

TY - JOUR

T1 - HEAT

T2 - Hierarchical Energy Analysis Tool

AU - Satyanarayana, Janardhan H.

AU - Parhi, Keshab K

PY - 1996/1/1

Y1 - 1996/1/1

N2 - This paper presents an algorithm for the estimation of power in static CMOS digital circuits using a stochastic approach. The salient feature of this approach is that it can be used to estimate the power of reasonably large digital circuits in a very short time, due to its hierarchical nature. Here, the given circuit is first partitioned into smaller sub-circuits. Then, the sub-circuits are modeled using state transition diagrams (stds), and the steady-state probabilities associated with the various states are computed by treating them as irreducible Markov chains. Finally, the energy associated with each sub-circuit is computed, and the total energy of the circuit is obtained by summing up the energies of its constituent sub-circuits. In the proposed hierarchical approach, the energies associated with various edges in a sub-circuit are calculated only once using SPICE and these values are used several times; this results in large savings in computation time. Another advantage of the proposed approach is that we can accommodate switching activities at the transistor level and not necessarily at gate or higher levels. Experimental results show that the estimated power is in close agreement with the actual power obtained from exhaustive SPICE simulations, but the computation time required by the proposed approach is orders of magnitude less than that of SPICE.

AB - This paper presents an algorithm for the estimation of power in static CMOS digital circuits using a stochastic approach. The salient feature of this approach is that it can be used to estimate the power of reasonably large digital circuits in a very short time, due to its hierarchical nature. Here, the given circuit is first partitioned into smaller sub-circuits. Then, the sub-circuits are modeled using state transition diagrams (stds), and the steady-state probabilities associated with the various states are computed by treating them as irreducible Markov chains. Finally, the energy associated with each sub-circuit is computed, and the total energy of the circuit is obtained by summing up the energies of its constituent sub-circuits. In the proposed hierarchical approach, the energies associated with various edges in a sub-circuit are calculated only once using SPICE and these values are used several times; this results in large savings in computation time. Another advantage of the proposed approach is that we can accommodate switching activities at the transistor level and not necessarily at gate or higher levels. Experimental results show that the estimated power is in close agreement with the actual power obtained from exhaustive SPICE simulations, but the computation time required by the proposed approach is orders of magnitude less than that of SPICE.

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M3 - Article

SP - 9

EP - 14

JO - Proceedings - Design Automation Conference

JF - Proceedings - Design Automation Conference

SN - 0738-100X

ER -