HARP: Hard-wired routing pattern FPGAs

Satish Sivaswamy, Gang Wang, Cristinel Ababei, Kia Bazargan, Ryan Kastner, Eli Bozorgzadeh

Research output: Contribution to conferencePaper

20 Scopus citations

Abstract

Modern FPGA architectures provide ample routing resources so that designs can be routed successfully. The routing architecture is designed to handle versatile connection configurations. However, providing such great flexibility comes at a high cost in terms of area, delay and power. We propose a new FPGA routing architecture 1 that utilizes a mixture of hard-wired and traditional flexible switches. The result is 24% reduction in leakage power consumption, 7% smaller area and 24% shorter delays, which translates to 30% increase in clock frequency. Despite the increase in clock speeds, the overall power consumption is reduced by 8%.

Original languageEnglish (US)
Pages21-29
Number of pages9
StatePublished - Jun 20 2005
EventACM/SIGDA Thirteenth ACM International Symposium on Field Programmable Gate Arrays - FPGA 2005 - Monterey, CA, United States
Duration: Feb 20 2005Feb 22 2005

Conference

ConferenceACM/SIGDA Thirteenth ACM International Symposium on Field Programmable Gate Arrays - FPGA 2005
CountryUnited States
CityMonterey, CA
Period2/20/052/22/05

Keywords

  • Design
  • Experimentation
  • Performance

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  • Cite this

    Sivaswamy, S., Wang, G., Ababei, C., Bazargan, K., Kastner, R., & Bozorgzadeh, E. (2005). HARP: Hard-wired routing pattern FPGAs. 21-29. Paper presented at ACM/SIGDA Thirteenth ACM International Symposium on Field Programmable Gate Arrays - FPGA 2005, Monterey, CA, United States.