HARP: Hard-wired routing pattern FPGAs

Satish Sivaswamy; Gang Wang; Cristinel Ababei; Kia Bazargan; Ryan Kastner; Eli Bozorgzadeh

HARP: Hard-wired routing pattern FPGAs

Satish Sivaswamy, Gang Wang, Cristinel Ababei, Kia Bazargan, Ryan Kastner, Eli Bozorgzadeh

Electrical and Computer Engineering

Research output: Contribution to conference › Paper › peer-review

27 Scopus citations

Abstract

Modern FPGA architectures provide ample routing resources so that designs can be routed successfully. The routing architecture is designed to handle versatile connection configurations. However, providing such great flexibility comes at a high cost in terms of area, delay and power. We propose a new FPGA routing architecture ¹ that utilizes a mixture of hard-wired and traditional flexible switches. The result is 24% reduction in leakage power consumption, 7% smaller area and 24% shorter delays, which translates to 30% increase in clock frequency. Despite the increase in clock speeds, the overall power consumption is reduced by 8%.

Original language	English (US)
Pages	21-29
Number of pages	9
State	Published - 2005
Event	ACM/SIGDA Thirteenth ACM International Symposium on Field Programmable Gate Arrays - FPGA 2005 - Monterey, CA, United States Duration: Feb 20 2005 → Feb 22 2005

Conference

Conference	ACM/SIGDA Thirteenth ACM International Symposium on Field Programmable Gate Arrays - FPGA 2005
Country/Territory	United States
City	Monterey, CA
Period	2/20/05 → 2/22/05

Keywords

Design
Experimentation
Performance

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title = "HARP: Hard-wired routing pattern FPGAs",

abstract = "Modern FPGA architectures provide ample routing resources so that designs can be routed successfully. The routing architecture is designed to handle versatile connection configurations. However, providing such great flexibility comes at a high cost in terms of area, delay and power. We propose a new FPGA routing architecture 1 that utilizes a mixture of hard-wired and traditional flexible switches. The result is 24% reduction in leakage power consumption, 7% smaller area and 24% shorter delays, which translates to 30% increase in clock frequency. Despite the increase in clock speeds, the overall power consumption is reduced by 8%.",

keywords = "Design, Experimentation, Performance",

author = "Satish Sivaswamy and Gang Wang and Cristinel Ababei and Kia Bazargan and Ryan Kastner and Eli Bozorgzadeh",

year = "2005",

language = "English (US)",

pages = "21--29",

note = "ACM/SIGDA Thirteenth ACM International Symposium on Field Programmable Gate Arrays - FPGA 2005 ; Conference date: 20-02-2005 Through 22-02-2005",

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T1 - HARP

T2 - ACM/SIGDA Thirteenth ACM International Symposium on Field Programmable Gate Arrays - FPGA 2005

AU - Sivaswamy, Satish

AU - Wang, Gang

AU - Ababei, Cristinel

AU - Bazargan, Kia

AU - Kastner, Ryan

AU - Bozorgzadeh, Eli

PY - 2005

Y1 - 2005

N2 - Modern FPGA architectures provide ample routing resources so that designs can be routed successfully. The routing architecture is designed to handle versatile connection configurations. However, providing such great flexibility comes at a high cost in terms of area, delay and power. We propose a new FPGA routing architecture 1 that utilizes a mixture of hard-wired and traditional flexible switches. The result is 24% reduction in leakage power consumption, 7% smaller area and 24% shorter delays, which translates to 30% increase in clock frequency. Despite the increase in clock speeds, the overall power consumption is reduced by 8%.

AB - Modern FPGA architectures provide ample routing resources so that designs can be routed successfully. The routing architecture is designed to handle versatile connection configurations. However, providing such great flexibility comes at a high cost in terms of area, delay and power. We propose a new FPGA routing architecture 1 that utilizes a mixture of hard-wired and traditional flexible switches. The result is 24% reduction in leakage power consumption, 7% smaller area and 24% shorter delays, which translates to 30% increase in clock frequency. Despite the increase in clock speeds, the overall power consumption is reduced by 8%.

KW - Design

KW - Experimentation

KW - Performance

UR - http://www.scopus.com/inward/record.url?scp=20344386500&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=20344386500&partnerID=8YFLogxK

M3 - Paper

AN - SCOPUS:20344386500

SP - 21

EP - 29

Y2 - 20 February 2005 through 22 February 2005

ER -

HARP: Hard-wired routing pattern FPGAs

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