Hardware efficient fast parallel FIR filter structures based on iterated short convolution

Chao Cheng, Keshab K. Parhi

Research output: Contribution to journalArticlepeer-review

75 Scopus citations

Abstract

This paper presents an Iterated Short Convolution (ISC) algorithm, based on the mixed radix algorithm and fast convolution algorithm. This ISC based linear convolution structure is transposed to obtain a new hardware efficient fast parallel FIR filter structure, which saves a large amount of hardware cost, especially when the length of the FIR filter is large. For example, for a 576-tap filter, the proposed structure saves 16.7% to 42.1% of the multiplications, 16.7% to 43.6% of the delay elements and 2.9% to 27% of the additions, which prior fast parallel structures use, when the level of parallelism varies from 6 to 72. These proposed structures exhibit regular structure.

Original languageEnglish (US)
Pages (from-to)1492-1500
Number of pages9
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Volume51
Issue number8
DOIs
StatePublished - 2004
Event2004 IEEE International Symposium on Cirquits and Systems - Proceedings - Vancouver, BC, Canada
Duration: May 23 2004May 26 2004

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