This paper presents an Iterated Short Convolution (ISC) algorithm, based on the mixed radix algorithm and fast convolution algorithm. This ISC based linear convolution structure is transposed to obtain a new hardware efficient fast parallel FIR filter structure, which saves a large amount of hardware cost, especially when the length of the FIR filter is large. For example, for a 576-tap filter, the proposed structure saves 16.7% to 42.1% of the multiplications, 16.7% to 43.6% of the delay elements and 2.9% to 27% of the additions, which prior fast parallel structures use, when the level of parallelism varies from 6 to 72. These proposed structures exhibit regular structure.
|Original language||English (US)|
|Number of pages||9|
|Journal||IEEE Transactions on Circuits and Systems I: Regular Papers|
|State||Published - 2004|
|Event||2004 IEEE International Symposium on Cirquits and Systems - Proceedings - Vancouver, BC, Canada|
Duration: May 23 2004 → May 26 2004