Hardware channel model for ultra wideband systems

Wen Chih Kan, Gerald E. Sobelman

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

We present a digital hardware model for ultra wideband channels. The system runs at 80 MMz on a Xilinx Virtex-4 xc4vsx35 FPGA. High-speed arithmetic operations including division, square root, powering and normal random number generator are analyzed and developed for use as basic components in the channel emulator. The design flow is based on Matlab Simulink as the model builder, followed by Xilinx System Generator to transform the Simulink model into a VHDL description which can be synthesized and mapped onto the FPGA device. Speed and area results are given for the synthesized designs.

Original languageEnglish (US)
Title of host publicationProceedings - 2006 IEEE International Conference on Field Programmable Technology, FPT 2006
Pages297-300
Number of pages4
DOIs
StatePublished - Dec 1 2006
Event2006 IEEE International Conference on Field Programmable Technology, FPT 2006 - Bangkok, Thailand
Duration: Dec 13 2006Dec 15 2006

Publication series

NameProceedings - 2006 IEEE International Conference on Field Programmable Technology, FPT 2006

Other

Other2006 IEEE International Conference on Field Programmable Technology, FPT 2006
CountryThailand
CityBangkok
Period12/13/0612/15/06

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    Kan, W. C., & Sobelman, G. E. (2006). Hardware channel model for ultra wideband systems. In Proceedings - 2006 IEEE International Conference on Field Programmable Technology, FPT 2006 (pp. 297-300). [4042454] (Proceedings - 2006 IEEE International Conference on Field Programmable Technology, FPT 2006). https://doi.org/10.1109/FPT.2006.270332