TY - GEN
T1 - Hardware channel model for ultra wideband systems
AU - Kan, Wen Chih
AU - Sobelman, Gerald E.
PY - 2006/12/1
Y1 - 2006/12/1
N2 - We present a digital hardware model for ultra wideband channels. The system runs at 80 MMz on a Xilinx Virtex-4 xc4vsx35 FPGA. High-speed arithmetic operations including division, square root, powering and normal random number generator are analyzed and developed for use as basic components in the channel emulator. The design flow is based on Matlab Simulink as the model builder, followed by Xilinx System Generator to transform the Simulink model into a VHDL description which can be synthesized and mapped onto the FPGA device. Speed and area results are given for the synthesized designs.
AB - We present a digital hardware model for ultra wideband channels. The system runs at 80 MMz on a Xilinx Virtex-4 xc4vsx35 FPGA. High-speed arithmetic operations including division, square root, powering and normal random number generator are analyzed and developed for use as basic components in the channel emulator. The design flow is based on Matlab Simulink as the model builder, followed by Xilinx System Generator to transform the Simulink model into a VHDL description which can be synthesized and mapped onto the FPGA device. Speed and area results are given for the synthesized designs.
UR - http://www.scopus.com/inward/record.url?scp=43749114276&partnerID=8YFLogxK
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U2 - 10.1109/FPT.2006.270332
DO - 10.1109/FPT.2006.270332
M3 - Conference contribution
AN - SCOPUS:43749114276
SN - 0780397282
SN - 9780780397286
T3 - Proceedings - 2006 IEEE International Conference on Field Programmable Technology, FPT 2006
SP - 297
EP - 300
BT - Proceedings - 2006 IEEE International Conference on Field Programmable Technology, FPT 2006
T2 - 2006 IEEE International Conference on Field Programmable Technology, FPT 2006
Y2 - 13 December 2006 through 15 December 2006
ER -