Hardware accelerator for linguistic data processing

Marian S. Stachowicz, Janos Grantner, Larry L. Kinney

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A hardware accelerator that performs fuzzy learning, fuzzy inference, and defuzzification strategy computations is presented in this paper. The hardware is based on two-valued logic. A universal space of 25 elements with five levels each is supported. To achieve a high processing rate for real-time applications, the basic units of the accelerator are connected in a four-level pipeline. The accelerator can receive two parallel fuzzy data as inputs. At a clock rate of 20 MHz, the accelerator can perform 800,000 fuzzy logic inferences per second on multidimensional fuzzy data.

Original languageEnglish (US)
Title of host publicationProceedings of SPIE - The International Society for Optical Engineering
EditorsDavid P. Casasent
PublisherPubl by Int Soc for Optical Engineering
Pages439-445
Number of pages7
ISBN (Print)0819407445
StatePublished - Jan 1 1992
EventIntelligent Robots and Computer Vision X: Algorithms and Techniques - Boston, MA, USA
Duration: Nov 11 1991Nov 13 1991

Publication series

NameProceedings of SPIE - The International Society for Optical Engineering
Volume1607
ISSN (Print)0277-786X

Other

OtherIntelligent Robots and Computer Vision X: Algorithms and Techniques
CityBoston, MA, USA
Period11/11/9111/13/91

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