| Original language | English (US) |
|---|---|
| Pages (from-to) | 496-497 |
| Number of pages | 2 |
| Journal | IEEE Design and Test of Computers |
| Volume | 22 |
| Issue number | 6 |
| DOIs | |
| State | Published - Nov 2005 |
Bibliographical note
Funding Information:and Marjorie Henle Professor in the Department of Electrical and Comput- er Engineering at the University of Min-nesota. His research interests include timing, layout, and 3D integration. Sapatnekar has a BTech from the Indian Institute of Technology, Bombay, an MS from Syracuse University, and a PhD from the University of Illinois, Urbana-Champaign. He has received the NSF Career award, the SRC Technical Excellence award, and best paper awards from the Design Automation Conference and the IEEE International Conference on Computer Design. He is a Fellow of the IEEE and a member of the ACM.