Abstract
Gracefully degrading multiprocessor systems are studied, using a multistage interconnection network-based system as an example. A measure of graceful degradation, called system integrity level, which is proportional to the number of different data flow paths in a system in presence of faults, is introduced; its properties are analyzed. It is shown that under this approach, graceful degradation of multiprocessor system can be evaluated as a combination of individual degradations in each of the processor, memory, and network subsystems.
| Original language | English (US) |
|---|---|
| Title of host publication | Proceedings of the International Conference on Parallel Processing |
| Editors | Sartaj K. Sahni |
| Publisher | Pennsylvania State Univ Press |
| Pages | 885-888 |
| Number of pages | 4 |
| ISBN (Print) | 0271006080 |
| State | Published - Dec 1 1987 |
| Event | Proc Int Conf Parallel Process 1987 - Universal Park, PA, USA Duration: Aug 17 1987 → Aug 21 1987 |
Other
| Other | Proc Int Conf Parallel Process 1987 |
|---|---|
| City | Universal Park, PA, USA |
| Period | 8/17/87 → 8/21/87 |