TY - GEN
T1 - GNOMO
T2 - 17th Asia and South Pacific Design Automation Conference, ASP-DAC 2012
AU - Gupta, Saket
AU - Sapatnekar, Sachin S
PY - 2012
Y1 - 2012
N2 - This paper presents a novel scheme for mitigating delay degradations in digital circuits due to bias temperature instability (BTI). The method works in two alternating phases. In the first, a greater-than-nominal supply voltage, V dd,g is used, which causes a task to complete more quickly but causes greater aging than the nominal supply voltage, V dd,n. In the second, the circuit is power-gated, enabling the BTI recovery phase. We demonstrate, both at the circuit and the architectural levels, that this approach can significantly mitigate aging for a small performance penalty.
AB - This paper presents a novel scheme for mitigating delay degradations in digital circuits due to bias temperature instability (BTI). The method works in two alternating phases. In the first, a greater-than-nominal supply voltage, V dd,g is used, which causes a task to complete more quickly but causes greater aging than the nominal supply voltage, V dd,n. In the second, the circuit is power-gated, enabling the BTI recovery phase. We demonstrate, both at the circuit and the architectural levels, that this approach can significantly mitigate aging for a small performance penalty.
UR - http://www.scopus.com/inward/record.url?scp=84859996302&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84859996302&partnerID=8YFLogxK
U2 - 10.1109/ASPDAC.2012.6164957
DO - 10.1109/ASPDAC.2012.6164957
M3 - Conference contribution
AN - SCOPUS:84859996302
SN - 9781467307727
T3 - Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
SP - 271
EP - 276
BT - ASP-DAC 2012 - 17th Asia and South Pacific Design Automation Conference
Y2 - 30 January 2012 through 2 February 2012
ER -