Gate size optimization for row-based layouts

Naresh Maheshwari, Sachin S. Sapatnekar

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

A transistor sizing algorithm for row-based layouts is presented under a improved area model. This algorithm uses convex programming to find a minimal area circuit for a given delay specification. The new area model uses a concept of row heights as opposed to the conventional metric of sum of gate sizes. Results over a number of circuit indicate a significant reduction both in the minimum delay achievable and area as compared to TILOS-like optimizer.

Original languageEnglish (US)
Title of host publicationMidwest Symposium on Circuits and Systems
PublisherIEEE
Pages777-780
Number of pages4
Volume2
StatePublished - Dec 1 1995
EventProceedings of the 1995 IEEE 38th Midwest Symposium on Circuits and Systems. Part 1 (of 2) - Rio de Janeiro, Braz
Duration: Aug 13 1995Aug 16 1995

Other

OtherProceedings of the 1995 IEEE 38th Midwest Symposium on Circuits and Systems. Part 1 (of 2)
CityRio de Janeiro, Braz
Period8/13/958/16/95

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