Abstract
A transistor sizing algorithm for row-based layouts is presented under a improved area model. This algorithm uses convex programming to find a minimal area circuit for a given delay specification. The new area model uses a concept of row heights as opposed to the conventional metric of sum of gate sizes. Results over a number of circuit indicate a significant reduction both in the minimum delay achievable and area as compared to TILOS-like optimizer.
| Original language | English (US) |
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| Title of host publication | Midwest Symposium on Circuits and Systems |
| Publisher | IEEE |
| Pages | 777-780 |
| Number of pages | 4 |
| Volume | 2 |
| State | Published - Dec 1 1995 |
| Event | Proceedings of the 1995 IEEE 38th Midwest Symposium on Circuits and Systems. Part 1 (of 2) - Rio de Janeiro, Braz Duration: Aug 13 1995 → Aug 16 1995 |
Other
| Other | Proceedings of the 1995 IEEE 38th Midwest Symposium on Circuits and Systems. Part 1 (of 2) |
|---|---|
| City | Rio de Janeiro, Braz |
| Period | 8/13/95 → 8/16/95 |