Gate Leakage Reduction for Scaled Devices Using Transistor Stacking

Saibal Mukhopadhyay, Cassondra Neau, Riza Tamer Cakici, Amit Agarwal, Chris H. Kim, Kaushik Roy

Research output: Contribution to journalArticlepeer-review

126 Scopus citations

Abstract

In this paper, the effect of gate tunneling current in ultra-thin gate oxide MOS devices of effective length (Leff) of 25 nm (oxide thickness = 1.1 nm), 50 nm (oxide thickness = 1.5 nm) and 90 nm (oxide thickness = 2.5 nm) is studied using device simulation. Overall leakage in a stack of transistors is modeled and the opportunities for leakage reduction in the standby mode of operation are explored for scaled technologies. It is shown that, as the contribution of gate leakage relative to the total leakage increases with technology scaling, traditional techniques become ineffective in reducing overall leakage current in a circuit. A novel technique of input vector selection based on the relative contributions of gate and subthreshold leakage to the overall leakage is proposed for reducing total leakage in a circuit. This technique results in 44% savings in total leakage in 50-nm devices compared to the conventional stacking technique.

Original languageEnglish (US)
Pages (from-to)716-730
Number of pages15
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume11
Issue number4
DOIs
StatePublished - Aug 2003

Bibliographical note

Funding Information:
Manuscript received October 17, 2002; revised January 18, 2003. This work is supported in part by the Semiconductor Research Corporation, and in part by the Defense Advanced Research Program Agency, Intel, and IBM.

Keywords

  • Device simulation
  • Gate direct tunneling
  • Standby-mode
  • Subthreshold leakage
  • Technology scaling
  • Transistor stacking
  • Ultra-thin gate oxide

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