Automated subcircuit identification and annotation enables the creation of hierarchical representations of analog netlists, and can facilitate a variety of design automation tasks such as circuit layout and optimization. Subcircuit identification must navigate the numerous alternative structures that can implement any analog function, but traditional graph-based methods cannot easily identify the large number of such structural variants. The novel approach in this paper is based on the use of a trained graph convolutional neural network (GCN) that identifies netlist elements for circuit blocks at upper levels of the design hierarchy. Structures at lower levels of hierarchy are identified using graph-based algorithms. The proposed recognition scheme organically detects layout constraints, such as symmetry and matching, whose identification is essential for high-quality hierarchical layout. The subcircuit identification method demonstrates a high degree of accuracy over a wide range of analog designs, successfully identifies larger circuits that contain subblocks such as OTAs, LNAs, mixers, oscillators, and band-pass filters, and provides hierarchical decompositions of such circuits.
|Original language||English (US)|
|Title of host publication||Proceedings of the 2020 Design, Automation and Test in Europe Conference and Exhibition, DATE 2020|
|Editors||Giorgio Di Natale, Cristiana Bolchini, Elena-Ioana Vatajelu|
|Publisher||Institute of Electrical and Electronics Engineers Inc.|
|Number of pages||6|
|State||Published - Mar 2020|
|Event||2020 Design, Automation and Test in Europe Conference and Exhibition, DATE 2020 - Grenoble, France|
Duration: Mar 9 2020 → Mar 13 2020
|Name||Proceedings of the 2020 Design, Automation and Test in Europe Conference and Exhibition, DATE 2020|
|Conference||2020 Design, Automation and Test in Europe Conference and Exhibition, DATE 2020|
|Period||3/9/20 → 3/13/20|
Bibliographical notePublisher Copyright:
© 2020 EDAA.