Fully parallel write/read in resistive synaptic array for accelerating on-chip learning

Ligang Gao, I. Ting Wang, Pai Yu Chen, Sarma Vrudhula, Jae Sun Seo, Yu Cao, Tuo Hung Hou, Shimeng Yu

Research output: Contribution to journalArticlepeer-review

111 Scopus citations


A neuro-inspired computing paradigm beyond the von Neumann architecture is emerging and it generally takes advantage of massive parallelism and is aimed at complex tasks that involve intelligence and learning. The cross-point array architecture with synaptic devices has been proposed for on-chip implementation of the weighted sum and weight update in the learning algorithms. In this work, forming-free, silicon-process-compatible Ta/TaO x /TiO2/Ti synaptic devices are fabricated, in which >200 levels of conductance states could be continuously tuned by identical programming pulses. In order to demonstrate the advantages of parallelism of the cross-point array architecture, a novel fully parallel write scheme is designed and experimentally demonstrated in a small-scale crossbar array to accelerate the weight update in the training process, at a speed that is independent of the array size. Compared to the conventional row-by-row write scheme, it achieves >30 ×speed-up and >30 ×improvement in energy efficiency as projected in a large-scale array. If realistic synaptic device characteristics such as device variations are taken into an array-level simulation, the proposed array architecture is able to achieve ∼95% recognition accuracy of MNIST handwritten digits, which is close to the accuracy achieved by software using the ideal sparse coding algorithm.

Original languageEnglish (US)
Article number455204
Issue number45
StatePublished - Oct 22 2015
Externally publishedYes

Bibliographical note

Publisher Copyright:
© 2015 IOP Publishing Ltd.


  • cross-point array
  • neuro-inspired computing
  • online learning
  • resistive switching
  • synaptic device
  • weight update
  • weighted sum


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