This paper presents an adaptive all-digital ripple mitigation technique for fully integrated capacitive dc-dc converters. Ripple control is achieved using a two-pronged approach where coarse ripple control is achieved by varying the size of the bucket capacitance, and fine control is achieved by charge/discharge time modulation of the bucket capacitors used to transfer the charge between the input and output, both of which are completely digital techniques. A dual-loop control was used to achieve regulation and ripple control. The primary single-bound hysteretic control loop achieves voltage regulation and the secondary loop is responsible for ripple control. The dual-loop control modulates the charge/discharge pulse width in a hysteretic variable-frequency environment using a simple digital pulse width modulator. The fully integrated converter was implemented in IBM's 130-nm CMOS process. Ripple reduces from 98 to 30 mV, when ripple control secondary loop is enabled for a load of 0.3 V and 4 mA without significantly impacting the converter's core efficiency. Measurement results show constant ripple, independent of output voltage. The converter achieves a maximum efficiency of 70% for Vin = 1.3 V and Vout = 0.5 V and a maximum power density of 24.5 mW/mm2, including the areas for the decoupling capacitor. The maximum power density increases to 68 mW/mm2 if the decoupling capacitor is assumed to be already present as part of the digital design.
- Capacitance modulation
- Dynamic voltage scaling (DVS)
- Fully integrated capacitive converter
- Ripple mitigation
- Time modulation