Full-chip analysis of leakage power under process variations, including spatial correlations

Hongliang Chang, Sachin S Sapatnekar

Research output: Contribution to journalConference articlepeer-review

166 Scopus citations

Abstract

In this paper, we present a method for analyzing the leakage current, and hence the leakage power, of a circuit under process parameter variations that can include spatial correlations due to intra-chip variation. A lognormal distribution is used to approximate the leakage current of each gate and the total chip leakage is determined by summing up the lognormals. In this work, Both subthreshold leakage and gate tunneling leakage are considered. The proposed method is shown to be effective in predicting the CDF/PDF of the total chip leakage. The average errors for mean and sigma values are -1.3% and -4.1%.

Original languageEnglish (US)
Article number32.1
Pages (from-to)523-528
Number of pages6
JournalProceedings - Design Automation Conference
StatePublished - Dec 1 2005
Event42nd Design Automation Conference, DAC 2005 - Anaheim, CA, United States
Duration: Jun 13 2005Jun 17 2005

Keywords

  • Algorithm
  • Design
  • Performance
  • Reliability

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