Abstract
We propose a complete analog mixed-signal circuit design flow from specification to silicon with minimum human-in-the-loop interaction, and verify the flow in a 12nm FinFET CMOS process. The flow consists of three key elements: neural network (NN) modeling of the parameterized circuit component, a search algorithm based on NN models to determine its sizing, and layout automation. To reduce the required training data for NN model creation, we utilize transfer learning to improve the NN accuracy from a relatively small amount of post-layout/silicon data. To prove the concept, we use a voltage-controlled oscillator (VCO) as a test vehicle and demonstrate that our design methodology can accurately model the circuit and generate designs with a wide range of specifications. We show that circuit sizing based on the transfer learned NN model from silicon measurement data yields the most accurate results.
Original language | English (US) |
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Title of host publication | 2021 40th IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2021 - Proceedings |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
ISBN (Electronic) | 9781665445078 |
DOIs | |
State | Published - 2021 |
Event | 40th IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2021 - Munich, Germany Duration: Nov 1 2021 → Nov 4 2021 |
Publication series
Name | IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD |
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Volume | 2021-November |
ISSN (Print) | 1092-3152 |
Conference
Conference | 40th IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2021 |
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Country/Territory | Germany |
City | Munich |
Period | 11/1/21 → 11/4/21 |
Bibliographical note
Funding Information:The authors wish to acknowledge support from the DARPA POSH program (FA8650-18-2-7853) and program manager Serge Leef. We also thank Global Foundries for access to GF12LP technology. Qiaochu Zhang also acknowledges the funding support from the University of Southern California Provost’s Fellowship.
Funding Information:
The authors wish to acknowledge support from the DARPA POSH program (FA8650-18-2-7853) and program manager Serge Leef. We also thank Global Foundries for access to GF12LP technology. Qiaochu Zhang also acknowledges the funding support from the University of Southern California Provost?s Fellowship.
Publisher Copyright:
© 2021 IEEE
Keywords
- AMS circuit design automation
- Circuit modeling
- Layout automation
- Silicon verified CAD