TY - JOUR
T1 - Fresh look at retiming via clock skew optimization
AU - Deokar, Rahul B.
AU - Sapatnekar, Sachin S.
PY - 1995/1/1
Y1 - 1995/1/1
N2 - The introduction of clock skew at an edge-triggered flip-flop has an effect that is similar to the movement of the flip-flop across combinational logic module boundaries, and these are continuous and discrete optimizations with the same effect. While this fact has been recognized before, this work, for the first time, utilizes this information to find a minimum/specified period retiming efficiently. The clock period is guaranteed to be at most one gate delay larger than a tight lower bound on the optimal clock period; this bound is achievable using a combination of intentional skew and retiming. All ISCAS89 circuits can be retimed in a few minutes by this algorithm.
AB - The introduction of clock skew at an edge-triggered flip-flop has an effect that is similar to the movement of the flip-flop across combinational logic module boundaries, and these are continuous and discrete optimizations with the same effect. While this fact has been recognized before, this work, for the first time, utilizes this information to find a minimum/specified period retiming efficiently. The clock period is guaranteed to be at most one gate delay larger than a tight lower bound on the optimal clock period; this bound is achievable using a combination of intentional skew and retiming. All ISCAS89 circuits can be retimed in a few minutes by this algorithm.
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M3 - Article
AN - SCOPUS:0029233969
SN - 0738-100X
SP - 310
EP - 315
JO - Proceedings - Design Automation Conference
JF - Proceedings - Design Automation Conference
ER -