Abstract
Some recent PLL designs utilize a half-rate phase detector so that the VCO operates at a frequency that is one-half of the input data rate. In this paper, a technique is proposed to extend the half-rate phase detector structure to a rate of 1/2n, for integer n>1. The concept is explained using a rate 1/8 implementation and simulation results are presented to verify the scheme. These rate 1/2n phase detectors can be used to raise the maximum operating frequency of clock and data recovery circuits in a given CMOS process technology.
Original language | English (US) |
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Title of host publication | Proceedings - IEEE International SOC Conference, SOCC 2003 |
Editors | Dong S. Ha, Richard Auletta, John Chickanosky |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
Pages | 313-316 |
Number of pages | 4 |
ISBN (Electronic) | 0780381823, 9780780381827 |
DOIs | |
State | Published - 2003 |
Event | IEEE International SOC Conference, SOCC 2003 - Portland, United States Duration: Sep 17 2003 → Sep 20 2003 |
Publication series
Name | Proceedings - IEEE International SOC Conference, SOCC 2003 |
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Other
Other | IEEE International SOC Conference, SOCC 2003 |
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Country/Territory | United States |
City | Portland |
Period | 9/17/03 → 9/20/03 |
Bibliographical note
Publisher Copyright:© 2003 IEEE.
Keywords
- CMOS process
- CMOS technology
- Circuits
- Clocks
- Latches
- Optical fiber communication
- Phase detection
- Phase frequency detector
- Phase locked loops
- Voltage-controlled oscillators