FPGA-based FIR filters using digital-serial arithmetic

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Abstract

This paper describes the use of digit-serial arithmetic for compact and efficient implementations of real-time DSP applications on field programmable gate arrays (FPGAs). As an example, the implementation of a digit-serial 5-tap FIR filter on a Xilinx XC4010 FPGA is considered. An analysis of the performance comparison of several FIR filters is described. The results show that digit-serial designs with a digit-size of 2 bits have about 17% smaller area-time product than those of a bit-serial implementations.

Original languageEnglish (US)
Pages (from-to)225-228
Number of pages4
JournalProceedings of the Annual IEEE International ASIC Conference and Exhibit
StatePublished - Jan 1 1997
EventProceedings of the 1997 10th Annual IEEE International ASIC Conference and Exhibit - Portland, OR, USA
Duration: Sep 7 1997Sep 10 1997

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