FPGA-based FIR filters using digital-serial arithmetic

Hanho Lee; Gerald E Sobelman

FPGA-based FIR filters using digital-serial arithmetic

Hanho Lee, Gerald E Sobelman

Electrical and Computer Engineering

Research output: Contribution to journal › Conference article › peer-review

25 Scopus citations

Abstract

This paper describes the use of digit-serial arithmetic for compact and efficient implementations of real-time DSP applications on field programmable gate arrays (FPGAs). As an example, the implementation of a digit-serial 5-tap FIR filter on a Xilinx XC4010 FPGA is considered. An analysis of the performance comparison of several FIR filters is described. The results show that digit-serial designs with a digit-size of 2 bits have about 17% smaller area-time product than those of a bit-serial implementations.

Original language	English (US)
Pages (from-to)	225-228
Number of pages	4
Journal	Proceedings of the Annual IEEE International ASIC Conference and Exhibit
State	Published - Jan 1 1997
Event	Proceedings of the 1997 10th Annual IEEE International ASIC Conference and Exhibit - Portland, OR, USA Duration: Sep 7 1997 → Sep 10 1997

Find It

Find It at U of M Libraries

Cite this

@article{d1f7b511c2474184a946cdd175255309,

title = "FPGA-based FIR filters using digital-serial arithmetic",

abstract = "This paper describes the use of digit-serial arithmetic for compact and efficient implementations of real-time DSP applications on field programmable gate arrays (FPGAs). As an example, the implementation of a digit-serial 5-tap FIR filter on a Xilinx XC4010 FPGA is considered. An analysis of the performance comparison of several FIR filters is described. The results show that digit-serial designs with a digit-size of 2 bits have about 17% smaller area-time product than those of a bit-serial implementations.",

author = "Hanho Lee and Sobelman, {Gerald E}",

year = "1997",

month = jan,

day = "1",

language = "English (US)",

pages = "225--228",

journal = "Proceedings of the Annual IEEE International ASIC Conference and Exhibit",

issn = "1063-0988",

note = "Proceedings of the 1997 10th Annual IEEE International ASIC Conference and Exhibit ; Conference date: 07-09-1997 Through 10-09-1997",

}

TY - JOUR

T1 - FPGA-based FIR filters using digital-serial arithmetic

AU - Lee, Hanho

AU - Sobelman, Gerald E

PY - 1997/1/1

Y1 - 1997/1/1

N2 - This paper describes the use of digit-serial arithmetic for compact and efficient implementations of real-time DSP applications on field programmable gate arrays (FPGAs). As an example, the implementation of a digit-serial 5-tap FIR filter on a Xilinx XC4010 FPGA is considered. An analysis of the performance comparison of several FIR filters is described. The results show that digit-serial designs with a digit-size of 2 bits have about 17% smaller area-time product than those of a bit-serial implementations.

AB - This paper describes the use of digit-serial arithmetic for compact and efficient implementations of real-time DSP applications on field programmable gate arrays (FPGAs). As an example, the implementation of a digit-serial 5-tap FIR filter on a Xilinx XC4010 FPGA is considered. An analysis of the performance comparison of several FIR filters is described. The results show that digit-serial designs with a digit-size of 2 bits have about 17% smaller area-time product than those of a bit-serial implementations.

UR - http://www.scopus.com/inward/record.url?scp=0030686379&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0030686379&partnerID=8YFLogxK

M3 - Conference article

AN - SCOPUS:0030686379

SN - 1063-0988

SP - 225

EP - 228

JO - Proceedings of the Annual IEEE International ASIC Conference and Exhibit

JF - Proceedings of the Annual IEEE International ASIC Conference and Exhibit

T2 - Proceedings of the 1997 10th Annual IEEE International ASIC Conference and Exhibit

Y2 - 7 September 1997 through 10 September 1997

ER -

FPGA-based FIR filters using digital-serial arithmetic

Abstract

Find It

Other files and links

Fingerprint

Cite this