FPGA-based digit-serial Complex Number Multiplier-Accumulator

T. Sansaloni, J. Valls, K. K. Parhi

Research output: Contribution to journalArticlepeer-review

1 Scopus citations


This paper presents a FPGA implementation of digit-serial Complex Number Multiplier-Accumulators (CMACs) based on Booth recoding techniques and Carry Save (CS) adders. The Complex Number Multiplier-Accumulators can be pipelined at LUT-level. An efficient mapping of the Booth recoding and the partial product generation is presented which results in a logic depth reduction. The combination of 5-3 and 4-3 converter in the CS structure and the utilization of Ripple Carry Adder (RCA) trees lead to a minimum area requirement.

Original languageEnglish (US)
Pages (from-to)IV-585-IV-588
JournalProceedings - IEEE International Symposium on Circuits and Systems
StatePublished - 2000


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