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FORC: A High-Throughput Streaming FPGA Accelerator for Optimized Row Columnar File Decoders in Big Data Engines

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

To improve the file storage efficiency of large datasets, big data analytics usually use some common file formats, such as Apache ORC (optimized row columnar) format, to encode and compress the data. However, this shifts the IO bottleneck (especially with high-bandwidth SSDs) to the computation bottleneck on CPUs to decompress and decode the data. This paper presents FORC, a high-throughput streaming-based FPGA accelerator overlay that supports different ORC file format decoders, and its dataflow integration with Apache ORC. Experimental results show that FORC achieves up to 12.9 GB/s decoding throughput on AMD/Xilinx Alveo U280 FPGA, with a geomean speedup of 65x (up to 335x) over the CPU. FORC will be released soon at https://github.com/SFU-HiAccel/FORC.

Original languageEnglish (US)
Title of host publicationProceedings - 2024 34th International Conference on Field-Programmable Logic and Applications, FPL 2024
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages318-324
Number of pages7
ISBN (Electronic)9798331530075
DOIs
StatePublished - 2024
Externally publishedYes
Event34th International Conference on Field-Programmable Logic and Applications, FPL 2024 - Torino, Italy
Duration: Sep 2 2024 → Sep 6 2024

Publication series

NameProceedings - 2024 34th International Conference on Field-Programmable Logic and Applications, FPL 2024

Conference

Conference34th International Conference on Field-Programmable Logic and Applications, FPL 2024
Country/TerritoryItaly
CityTorino
Period9/2/24 → 9/6/24

Bibliographical note

Publisher Copyright:
© 2024 IEEE.

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