Abstract
A parallel formulation of a branch-and-bound algorithm for floorplan optimization in VLSI design is given. Implementation details and performance analyses of the authors' formulation are presented. This implementation was done on a 128-node Symult s2010 multicomputer, as well as on a network of 16 SUN workstations. In the experiments with realistic problems, linear speedups on both machine configurations were obtained. Previous analyses of a similar parallel algorithm suggest that linear speedup can be obtained even on very large computers (>1000 processors) on practical instances of this problem.
| Original language | English (US) |
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| Title of host publication | Proceedings - IEEE International Conference on Computer Design |
| Subtitle of host publication | VLSI in Computers and Processors |
| Editors | Anon |
| Publisher | Publ by IEEE |
| Pages | 109-114 |
| Number of pages | 6 |
| State | Published - Dec 1 1989 |
| Event | Proceedings - 1989 IEEE International Conference on Computer Design: VLSI in Computers & Processors - Cambridge, MA, USA Duration: Oct 2 1989 → Oct 4 1989 |
Other
| Other | Proceedings - 1989 IEEE International Conference on Computer Design: VLSI in Computers & Processors |
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| City | Cambridge, MA, USA |
| Period | 10/2/89 → 10/4/89 |