Flexible LDPC decoder architecture for high-throughput applications

Keyphrases

• High-throughput 100%
• Node-based Approach 100%
• Code Rate 100%
• Block Size 100%
• High-speed Applications 100%
• LDPC Decoder Architecture 100%
• Code Block 100%
• Check Node 100%
• IEEE 802.16 50%
• LDPC Codes 50%
• Proposed Architecture 50%
• System Flexibility 50%
• Scheduling Scheme 50%
• Wireless Applications 50%
• Memory Bank 50%
• Layered Decoding 50%
• IEEE 802.11n 50%
• Serial Scheduling 50%
• IEEE 802.15.3c 50%
• LDPC Decoder 50%
• Parallel Scheduling 50%
• Fully Parallel Architecture 50%
• Decoding Method 50%

Computer Science

• High Throughput 100%
• Parallel Architectures 33%
• Scheduling Scheme 33%
• Parallel Block 33%