TY - GEN
T1 - Flexible LDPC decoder architecture for high-throughput applications
AU - Kim, Sangmin
AU - Sobelman, Gerald E
AU - Lee, Hanho
PY - 2008
Y1 - 2008
N2 - In this paper, we present a flexible high-throughput LDPC decoder architecture that can support different code rates and block sizes in wireless applications such as IEEE 802.11n, IEEE 802.16e, and IEEE 802.15.3c standards. Several flexible LDPC decoders have been presented in the literature but their throughput (less than 640 Mbps) is limited due to block-serial scheduling of the decoding computations. The proposed architecture is based on a block-parallel scheduling scheme using a layered decoding method. To achieve higher throughput, check node-based processes are implemented in a fully parallel architecture and the memory is partitioned into a number of banks. System flexibility is achieved by allowing the check node-based units and the memory banks to be configured according to the code rate and block size of the LDPC code of interest.
AB - In this paper, we present a flexible high-throughput LDPC decoder architecture that can support different code rates and block sizes in wireless applications such as IEEE 802.11n, IEEE 802.16e, and IEEE 802.15.3c standards. Several flexible LDPC decoders have been presented in the literature but their throughput (less than 640 Mbps) is limited due to block-serial scheduling of the decoding computations. The proposed architecture is based on a block-parallel scheduling scheme using a layered decoding method. To achieve higher throughput, check node-based processes are implemented in a fully parallel architecture and the memory is partitioned into a number of banks. System flexibility is achieved by allowing the check node-based units and the memory banks to be configured according to the code rate and block size of the LDPC code of interest.
UR - http://www.scopus.com/inward/record.url?scp=62949152337&partnerID=8YFLogxK
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U2 - 10.1109/APCCAS.2008.4745956
DO - 10.1109/APCCAS.2008.4745956
M3 - Conference contribution
AN - SCOPUS:62949152337
SN - 9781424423422
T3 - IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS
SP - 45
EP - 48
BT - Proceedings of APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems
T2 - APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems
Y2 - 30 November 2008 through 3 December 2008
ER -