TY - GEN
T1 - Finite-point gate model for fast timing and power analysis
AU - Ganesan, Dinesh
AU - Mitev, Alex
AU - Wang, Janet
AU - Cao, Yu
PY - 2008
Y1 - 2008
N2 - This paper proposes a new finite-point based approach for efficient characterization of CMOS gate. The new method identifies several key points on the I-V and Q-V curves to define the behavior of the static CMOS gate. It targets performance metrics such as timing, short-circuit power and leakage in the presence of process variations. Experimental results validate the accuracy of the new approach and yields simulation speeds more than 15X faster than BSIM based library characterization.
AB - This paper proposes a new finite-point based approach for efficient characterization of CMOS gate. The new method identifies several key points on the I-V and Q-V curves to define the behavior of the static CMOS gate. It targets performance metrics such as timing, short-circuit power and leakage in the presence of process variations. Experimental results validate the accuracy of the new approach and yields simulation speeds more than 15X faster than BSIM based library characterization.
UR - http://www.scopus.com/inward/record.url?scp=49749097946&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=49749097946&partnerID=8YFLogxK
U2 - 10.1109/ISQED.2008.4479815
DO - 10.1109/ISQED.2008.4479815
M3 - Conference contribution
AN - SCOPUS:49749097946
SN - 0769531172
SN - 9780769531175
T3 - Proceedings of the 9th International Symposium on Quality Electronic Design, ISQED 2008
SP - 657
EP - 662
BT - Proceedings of the 9th International Symposium on Quality Electronic Design, ISQED 2008
T2 - 9th International Symposium on Quality Electronic Design, ISQED 2008
Y2 - 17 March 2008 through 19 March 2008
ER -