TY - GEN
T1 - FFT implementation with multi-operand floating point units
AU - Zhang, Zhang
AU - Wang, Dongge
AU - Pan, Yuteng
AU - Wang, Dan
AU - Zhou, Xiaofang
AU - Sobelman, Gerald E.
PY - 2011
Y1 - 2011
N2 - In this paper we propose two new design techniques for floating point arithmetic units used in DSP applications, and apply them in the design of two multi-operand units for high-radix FFTs. These two multi-operand arithmetic units are a Modified two term Dot Product (MDP) unit and a Multi-operand Add-Sub unit (MAS). A radix-4 FFT butterfly computation block is implemented efficiently with these multi-operand units. Synthesis results show that the butterfly unit built with our design is about 43% faster and 9.5% smaller than a conventional implementation.
AB - In this paper we propose two new design techniques for floating point arithmetic units used in DSP applications, and apply them in the design of two multi-operand units for high-radix FFTs. These two multi-operand arithmetic units are a Modified two term Dot Product (MDP) unit and a Multi-operand Add-Sub unit (MAS). A radix-4 FFT butterfly computation block is implemented efficiently with these multi-operand units. Synthesis results show that the butterfly unit built with our design is about 43% faster and 9.5% smaller than a conventional implementation.
KW - Floating-point Arithmetic
KW - Multi-operand Floating-point operations
KW - Radix-4 FFT Butterfly
UR - https://www.scopus.com/pages/publications/84860875897
UR - https://www.scopus.com/pages/publications/84860875897#tab=citedBy
U2 - 10.1109/ASICON.2011.6157160
DO - 10.1109/ASICON.2011.6157160
M3 - Conference contribution
AN - SCOPUS:84860875897
SN - 9781612841908
T3 - Proceedings of International Conference on ASIC
SP - 216
EP - 219
BT - Proceedings - 2011 IEEE 9th International Conference on ASIC, ASICON 2011
T2 - 2011 IEEE 9th International Conference on ASIC, ASICON 2011
Y2 - 25 October 2011 through 28 October 2011
ER -