FFT implementation with multi-operand floating point units

Zhang Zhang, Dongge Wang, Yuteng Pan, Dan Wang, Xiaofang Zhou, Gerald E Sobelman

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Scopus citations

Abstract

In this paper we propose two new design techniques for floating point arithmetic units used in DSP applications, and apply them in the design of two multi-operand units for high-radix FFTs. These two multi-operand arithmetic units are a Modified two term Dot Product (MDP) unit and a Multi-operand Add-Sub unit (MAS). A radix-4 FFT butterfly computation block is implemented efficiently with these multi-operand units. Synthesis results show that the butterfly unit built with our design is about 43% faster and 9.5% smaller than a conventional implementation.

Original languageEnglish (US)
Title of host publicationProceedings - 2011 IEEE 9th International Conference on ASIC, ASICON 2011
Pages216-219
Number of pages4
DOIs
StatePublished - Dec 1 2011
Event2011 IEEE 9th International Conference on ASIC, ASICON 2011 - Xiamen, China
Duration: Oct 25 2011Oct 28 2011

Publication series

NameProceedings of International Conference on ASIC
ISSN (Print)2162-7541
ISSN (Electronic)2162-755X

Other

Other2011 IEEE 9th International Conference on ASIC, ASICON 2011
CountryChina
CityXiamen
Period10/25/1110/28/11

Keywords

  • Floating-point Arithmetic
  • Multi-operand Floating-point operations
  • Radix-4 FFT Butterfly

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    Zhang, Z., Wang, D., Pan, Y., Wang, D., Zhou, X., & Sobelman, G. E. (2011). FFT implementation with multi-operand floating point units. In Proceedings - 2011 IEEE 9th International Conference on ASIC, ASICON 2011 (pp. 216-219). [6157160] (Proceedings of International Conference on ASIC). https://doi.org/10.1109/ASICON.2011.6157160