FFT architectures for real-valued signals based on radix-23 and Radix-24 algorithms

Manohar Ayinala, Keshab K Parhi

Research output: Contribution to journalArticle

31 Citations (Scopus)

Abstract

This paper presents a novel approach to develop pipelined fast Fourier transform (FFT) architectures for real-valued signals. The proposed methodology is based on modifying the flow graph of the FFT algorithm such that it has both real and complex datapaths. The imaginary parts of the computations replace the redundant operations in the modified flow graph. New butterfly structures are designed to handle the hybrid datapaths. The proposed hybrid datapath leads to a general approach which can be extended to all radix-2n based FFT algorithms. Further, architectures with arbitrary level of parallelism can be derived using the folding methodology. Novel 2-parallel and 4-parallel architectures are presented for radix-23 and radix-24 algorithms. The proposed architectures maximize the utilization of hardware components with no redundant computations. The proposed radix-23 and radix-24 architectures lead to low hardware complexity with respect to adders and delays. The N-point 4-parallel radix-24 architecture requires 2(log16N-1) complex multipliers, 2log2N real adders and N complex delay elements.

Original languageEnglish (US)
Article number6466397
Pages (from-to)2422-2430
Number of pages9
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Volume60
Issue number9
DOIs
StatePublished - Feb 26 2013

Fingerprint

Fast Fourier transforms
Flow graphs
Adders
Hardware
Parallel architectures

Keywords

  • Decimation-in-frequency (DIF)
  • fast Fourier transfrom (FFT)
  • parallel
  • pipelining
  • radix-2
  • radix-2
  • real-valued signals

Cite this

FFT architectures for real-valued signals based on radix-23 and Radix-24 algorithms. / Ayinala, Manohar; Parhi, Keshab K.

In: IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 60, No. 9, 6466397, 26.02.2013, p. 2422-2430.

Research output: Contribution to journalArticle

@article{b8e773f56c6646b2bcf900e18662f5bf,
title = "FFT architectures for real-valued signals based on radix-23 and Radix-24 algorithms",
abstract = "This paper presents a novel approach to develop pipelined fast Fourier transform (FFT) architectures for real-valued signals. The proposed methodology is based on modifying the flow graph of the FFT algorithm such that it has both real and complex datapaths. The imaginary parts of the computations replace the redundant operations in the modified flow graph. New butterfly structures are designed to handle the hybrid datapaths. The proposed hybrid datapath leads to a general approach which can be extended to all radix-2n based FFT algorithms. Further, architectures with arbitrary level of parallelism can be derived using the folding methodology. Novel 2-parallel and 4-parallel architectures are presented for radix-23 and radix-24 algorithms. The proposed architectures maximize the utilization of hardware components with no redundant computations. The proposed radix-23 and radix-24 architectures lead to low hardware complexity with respect to adders and delays. The N-point 4-parallel radix-24 architecture requires 2(log16N-1) complex multipliers, 2log2N real adders and N complex delay elements.",
keywords = "Decimation-in-frequency (DIF), fast Fourier transfrom (FFT), parallel, pipelining, radix-2, radix-2, real-valued signals",
author = "Manohar Ayinala and Parhi, {Keshab K}",
year = "2013",
month = "2",
day = "26",
doi = "10.1109/TCSI.2013.2246251",
language = "English (US)",
volume = "60",
pages = "2422--2430",
journal = "IEEE Transactions on Circuits and Systems I: Regular Papers",
issn = "1549-8328",
number = "9",

}

TY - JOUR

T1 - FFT architectures for real-valued signals based on radix-23 and Radix-24 algorithms

AU - Ayinala, Manohar

AU - Parhi, Keshab K

PY - 2013/2/26

Y1 - 2013/2/26

N2 - This paper presents a novel approach to develop pipelined fast Fourier transform (FFT) architectures for real-valued signals. The proposed methodology is based on modifying the flow graph of the FFT algorithm such that it has both real and complex datapaths. The imaginary parts of the computations replace the redundant operations in the modified flow graph. New butterfly structures are designed to handle the hybrid datapaths. The proposed hybrid datapath leads to a general approach which can be extended to all radix-2n based FFT algorithms. Further, architectures with arbitrary level of parallelism can be derived using the folding methodology. Novel 2-parallel and 4-parallel architectures are presented for radix-23 and radix-24 algorithms. The proposed architectures maximize the utilization of hardware components with no redundant computations. The proposed radix-23 and radix-24 architectures lead to low hardware complexity with respect to adders and delays. The N-point 4-parallel radix-24 architecture requires 2(log16N-1) complex multipliers, 2log2N real adders and N complex delay elements.

AB - This paper presents a novel approach to develop pipelined fast Fourier transform (FFT) architectures for real-valued signals. The proposed methodology is based on modifying the flow graph of the FFT algorithm such that it has both real and complex datapaths. The imaginary parts of the computations replace the redundant operations in the modified flow graph. New butterfly structures are designed to handle the hybrid datapaths. The proposed hybrid datapath leads to a general approach which can be extended to all radix-2n based FFT algorithms. Further, architectures with arbitrary level of parallelism can be derived using the folding methodology. Novel 2-parallel and 4-parallel architectures are presented for radix-23 and radix-24 algorithms. The proposed architectures maximize the utilization of hardware components with no redundant computations. The proposed radix-23 and radix-24 architectures lead to low hardware complexity with respect to adders and delays. The N-point 4-parallel radix-24 architecture requires 2(log16N-1) complex multipliers, 2log2N real adders and N complex delay elements.

KW - Decimation-in-frequency (DIF)

KW - fast Fourier transfrom (FFT)

KW - parallel

KW - pipelining

KW - radix-2

KW - radix-2

KW - real-valued signals

UR - http://www.scopus.com/inward/record.url?scp=84883462378&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84883462378&partnerID=8YFLogxK

U2 - 10.1109/TCSI.2013.2246251

DO - 10.1109/TCSI.2013.2246251

M3 - Article

VL - 60

SP - 2422

EP - 2430

JO - IEEE Transactions on Circuits and Systems I: Regular Papers

JF - IEEE Transactions on Circuits and Systems I: Regular Papers

SN - 1549-8328

IS - 9

M1 - 6466397

ER -