FEXT crosstalk cancellation for high-speed serial link design

Kin Joe Sham, Mahmoud Reza Ahmadi, Shubha Bommalingaiahnapallya, Gerry Talbot, Ramesh Harjani

Research output: Chapter in Book/Report/Conference proceedingConference contribution

26 Scopus citations

Abstract

We have proposed and verified an efficient architecture for a high-speed I/O transceiver design that implements far-end crosstalk (FEXT) cancellation. In this design, TX preemphasls, used traditionally to reduce ISI, is combined with FEXT cancellation at the transmitter to remove crosstalk-induced Jitter and interference. The architecture has been verified via simulation models based on channel measurement. A prototype implementation of a 12.8Gbps source-synchronous serial link transmitter has been developed in TSMCs 0.18μm CMOS technology. The proposed design consists of three 12.8Gbps data lines that uses a half-rate PLL clock of 6.4GHz. The chip includes a PRBS generator to simplify multi-lane testing. Simulation results show that, even with a 2X reduction in line separation, FEXT cancellation can successfully reduce Jitter by 51.2% UI and widen the eye by 14.5%. The 2.5×1.5 mm2 core consumes 630mW per lane at 12.8Gbps with a 1.8V supply.

Original languageEnglish (US)
Title of host publicationProceedings of the IEEE 2006 Custom Integrated Circuits Conference, CICC 2006
Pages405-408
Number of pages4
DOIs
StatePublished - Dec 1 2006
EventIEEE 2006 Custom Integrated Circuits Conference, CICC 2006 - San Jose, CA, United States
Duration: Sep 10 2006Sep 13 2006

Publication series

NameProceedings of the Custom Integrated Circuits Conference
ISSN (Print)0886-5930

Conference

ConferenceIEEE 2006 Custom Integrated Circuits Conference, CICC 2006
CountryUnited States
CitySan Jose, CA
Period9/10/069/13/06

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