TY - GEN
T1 - FEXT crosstalk cancellation for high-speed serial link design
AU - Sham, Kin Joe
AU - Ahmadi, Mahmoud Reza
AU - Bommalingaiahnapallya, Shubha
AU - Talbot, Gerry
AU - Harjani, Ramesh
PY - 2006
Y1 - 2006
N2 - We have proposed and verified an efficient architecture for a high-speed I/O transceiver design that implements far-end crosstalk (FEXT) cancellation. In this design, TX preemphasls, used traditionally to reduce ISI, is combined with FEXT cancellation at the transmitter to remove crosstalk-induced Jitter and interference. The architecture has been verified via simulation models based on channel measurement. A prototype implementation of a 12.8Gbps source-synchronous serial link transmitter has been developed in TSMCs 0.18μm CMOS technology. The proposed design consists of three 12.8Gbps data lines that uses a half-rate PLL clock of 6.4GHz. The chip includes a PRBS generator to simplify multi-lane testing. Simulation results show that, even with a 2X reduction in line separation, FEXT cancellation can successfully reduce Jitter by 51.2% UI and widen the eye by 14.5%. The 2.5×1.5 mm2 core consumes 630mW per lane at 12.8Gbps with a 1.8V supply.
AB - We have proposed and verified an efficient architecture for a high-speed I/O transceiver design that implements far-end crosstalk (FEXT) cancellation. In this design, TX preemphasls, used traditionally to reduce ISI, is combined with FEXT cancellation at the transmitter to remove crosstalk-induced Jitter and interference. The architecture has been verified via simulation models based on channel measurement. A prototype implementation of a 12.8Gbps source-synchronous serial link transmitter has been developed in TSMCs 0.18μm CMOS technology. The proposed design consists of three 12.8Gbps data lines that uses a half-rate PLL clock of 6.4GHz. The chip includes a PRBS generator to simplify multi-lane testing. Simulation results show that, even with a 2X reduction in line separation, FEXT cancellation can successfully reduce Jitter by 51.2% UI and widen the eye by 14.5%. The 2.5×1.5 mm2 core consumes 630mW per lane at 12.8Gbps with a 1.8V supply.
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U2 - 10.1109/CICC.2006.320971
DO - 10.1109/CICC.2006.320971
M3 - Conference contribution
AN - SCOPUS:39049170248
SN - 1424400767
SN - 9781424400768
T3 - Proceedings of the Custom Integrated Circuits Conference
SP - 405
EP - 408
BT - Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, CICC 2006
T2 - IEEE 2006 Custom Integrated Circuits Conference, CICC 2006
Y2 - 10 September 2006 through 13 September 2006
ER -