We have proposed and verified an efficient architecture for a high-speed I/O transceiver design that implements far-end crosstalk (FEXT) cancellation. In this design, TX preemphasls, used traditionally to reduce ISI, is combined with FEXT cancellation at the transmitter to remove crosstalk-induced Jitter and interference. The architecture has been verified via simulation models based on channel measurement. A prototype implementation of a 12.8Gbps source-synchronous serial link transmitter has been developed in TSMCs 0.18μm CMOS technology. The proposed design consists of three 12.8Gbps data lines that uses a half-rate PLL clock of 6.4GHz. The chip includes a PRBS generator to simplify multi-lane testing. Simulation results show that, even with a 2X reduction in line separation, FEXT cancellation can successfully reduce Jitter by 51.2% UI and widen the eye by 14.5%. The 2.5×1.5 mm2 core consumes 630mW per lane at 12.8Gbps with a 1.8V supply.