FET Fabricated by Layer-by-Layer Nanoassembly

Tianhong Cui, Feng Hua, Yuri Lvov

Research output: Contribution to journalArticlepeer-review

32 Scopus citations


Metal-oxide-semiconductor field-effect transistor (MOSFET) arrays are fabricated on a 4-in silicon wafer by the combination of conventional microelectronic processes and layer-by-layer nanofabrication. The active and insulating layers were self-assembled as organized multilayers of 15-nm diameter SnO2 and 45-nm diameter SiO2 nanoparticles, respectively. The source, drain, and gate electrodes are made of metal thin films. The threshold voltage is 3 V, on-off current ratio 104, and mobility 2.1 × 10-2 cm2 /V · s. This prototype leads to a new approach to fabricate low-cost MOSFETs and integrated circuits based on the layer-by-layer self-assembly of nanoparticles and charged macromolecules.

Original languageEnglish (US)
Pages (from-to)503-506
Number of pages4
JournalIEEE Transactions on Electron Devices
Issue number3
StatePublished - Mar 2004

Bibliographical note

Funding Information:
Manuscript received June 9, 2003; revised November 24, 2003. This work was supported in part by the National Science Found ation and the Louisiana Education Quality Support Fund under Grant NSF/LEQSF-0092001 and in part by the Louisiana Board of Regents und er Grant 2002-RDA19. The review of this brief was arranged by Ed itor S. Datta.


  • Field-effect transistor (FET)
  • Lithography
  • Nano self-assembly
  • Nanoparticle


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