FET Fabricated by Layer-by-Layer Nanoassembly

Tianhong Cui; Feng Hua; Yuri Lvov

doi:10.1109/TED.2003.822277

FET Fabricated by Layer-by-Layer Nanoassembly

Tianhong Cui, Feng Hua, Yuri Lvov

Mechanical Engineering

Research output: Contribution to journal › Article › peer-review

33 Scopus citations

Abstract

Metal-oxide-semiconductor field-effect transistor (MOSFET) arrays are fabricated on a 4-in silicon wafer by the combination of conventional microelectronic processes and layer-by-layer nanofabrication. The active and insulating layers were self-assembled as organized multilayers of 15-nm diameter SnO₂ and 45-nm diameter SiO₂ nanoparticles, respectively. The source, drain, and gate electrodes are made of metal thin films. The threshold voltage is 3 V, on-off current ratio 104, and mobility 2.1 × 10^-2 cm² /V · s. This prototype leads to a new approach to fabricate low-cost MOSFETs and integrated circuits based on the layer-by-layer self-assembly of nanoparticles and charged macromolecules.

Original language	English (US)
Pages (from-to)	503-506
Number of pages	4
Journal	IEEE Transactions on Electron Devices
Volume	51
Issue number	3
DOIs	https://doi.org/10.1109/TED.2003.822277
State	Published - Mar 2004

Bibliographical note

Funding Information:
Manuscript received June 9, 2003; revised November 24, 2003. This work was supported in part by the National Science Found ation and the Louisiana Education Quality Support Fund under Grant NSF/LEQSF-0092001 and in part by the Louisiana Board of Regents und er Grant 2002-RDA19. The review of this brief was arranged by Ed itor S. Datta.

Keywords

Field-effect transistor (FET)
Lithography
Nano self-assembly
Nanoparticle

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

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10.1109/TED.2003.822277

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title = "FET Fabricated by Layer-by-Layer Nanoassembly",

abstract = "Metal-oxide-semiconductor field-effect transistor (MOSFET) arrays are fabricated on a 4-in silicon wafer by the combination of conventional microelectronic processes and layer-by-layer nanofabrication. The active and insulating layers were self-assembled as organized multilayers of 15-nm diameter SnO2 and 45-nm diameter SiO2 nanoparticles, respectively. The source, drain, and gate electrodes are made of metal thin films. The threshold voltage is 3 V, on-off current ratio 104, and mobility 2.1 × 10-2 cm2 /V · s. This prototype leads to a new approach to fabricate low-cost MOSFETs and integrated circuits based on the layer-by-layer self-assembly of nanoparticles and charged macromolecules.",

keywords = "Field-effect transistor (FET), Lithography, Nano self-assembly, Nanoparticle",

author = "Tianhong Cui and Feng Hua and Yuri Lvov",

note = "Funding Information: Manuscript received June 9, 2003; revised November 24, 2003. This work was supported in part by the National Science Found ation and the Louisiana Education Quality Support Fund under Grant NSF/LEQSF-0092001 and in part by the Louisiana Board of Regents und er Grant 2002-RDA19. The review of this brief was arranged by Ed itor S. Datta.",

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AU - Cui, Tianhong

AU - Hua, Feng

AU - Lvov, Yuri

N1 - Funding Information: Manuscript received June 9, 2003; revised November 24, 2003. This work was supported in part by the National Science Found ation and the Louisiana Education Quality Support Fund under Grant NSF/LEQSF-0092001 and in part by the Louisiana Board of Regents und er Grant 2002-RDA19. The review of this brief was arranged by Ed itor S. Datta.

PY - 2004/3

Y1 - 2004/3

N2 - Metal-oxide-semiconductor field-effect transistor (MOSFET) arrays are fabricated on a 4-in silicon wafer by the combination of conventional microelectronic processes and layer-by-layer nanofabrication. The active and insulating layers were self-assembled as organized multilayers of 15-nm diameter SnO2 and 45-nm diameter SiO2 nanoparticles, respectively. The source, drain, and gate electrodes are made of metal thin films. The threshold voltage is 3 V, on-off current ratio 104, and mobility 2.1 × 10-2 cm2 /V · s. This prototype leads to a new approach to fabricate low-cost MOSFETs and integrated circuits based on the layer-by-layer self-assembly of nanoparticles and charged macromolecules.

AB - Metal-oxide-semiconductor field-effect transistor (MOSFET) arrays are fabricated on a 4-in silicon wafer by the combination of conventional microelectronic processes and layer-by-layer nanofabrication. The active and insulating layers were self-assembled as organized multilayers of 15-nm diameter SnO2 and 45-nm diameter SiO2 nanoparticles, respectively. The source, drain, and gate electrodes are made of metal thin films. The threshold voltage is 3 V, on-off current ratio 104, and mobility 2.1 × 10-2 cm2 /V · s. This prototype leads to a new approach to fabricate low-cost MOSFETs and integrated circuits based on the layer-by-layer self-assembly of nanoparticles and charged macromolecules.

KW - Field-effect transistor (FET)

KW - Lithography

KW - Nano self-assembly

KW - Nanoparticle

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DO - 10.1109/TED.2003.822277

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JO - IEEE Transactions on Electron Devices

JF - IEEE Transactions on Electron Devices

IS - 3

ER -

FET Fabricated by Layer-by-Layer Nanoassembly

Abstract

Bibliographical note

Keywords

UN SDGs

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