Abstract
During hierarchical design, it becomes essential at each level of the hierarchy to evaluate if a sub-block design is feasible and if so which design style is the best candidate for the particular problem. We propose a general methodology for evaluating the feasibility and the performance of sub-blocks at all levels of the hierarchy. In this paper we concentrate on techniques to model the feasibility region. The methodology is general and can be used for both analog and digital circuits. Macromodels are developed and verified for analog blocks at different levels of hierarchy.
Original language | English (US) |
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Pages | 407-410 |
Number of pages | 4 |
State | Published - Dec 1 1994 |
Event | Proceedings of the 37th Midwest Symposium on Circuits and Systems. Part 2 (of 2) - Lafayette, LA, USA Duration: Aug 3 1994 → Aug 5 1994 |
Other
Other | Proceedings of the 37th Midwest Symposium on Circuits and Systems. Part 2 (of 2) |
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City | Lafayette, LA, USA |
Period | 8/3/94 → 8/5/94 |