Feasibility analysis of the fixed-width pulse RZ feedback to reduce clock jitter effects in lowpass continuous-time ΔΣ modulators

Hairong Chang, Hua Tang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

A recently proposed method to reduce clock jitter effects in continuous-time Delta-Sigma modulators is to generate a return-to-zero feedback with a fixed-width pulse for active feedback. In practice, the pulse width is subject to noise effects causing jitter of the pulse width itself. Therefore, jitter of the pulse width, though not the clock, may still degrade the performance of Delta-Sigma modulators. In this brief, we investigate practical feasibility of the method. It is shown that jitter of the pulse width could be conditionally much smaller than that of the clock, which therefore reduces clock jitter effects.

Original languageEnglish (US)
Title of host publication2013 IEEE 56th International Midwest Symposium on Circuits and Systems, MWSCAS 2013
Pages245-248
Number of pages4
DOIs
StatePublished - Dec 1 2013
Event2013 IEEE 56th International Midwest Symposium on Circuits and Systems, MWSCAS 2013 - Columbus, OH, United States
Duration: Aug 4 2013Aug 7 2013

Other

Other2013 IEEE 56th International Midwest Symposium on Circuits and Systems, MWSCAS 2013
CountryUnited States
CityColumbus, OH
Period8/4/138/7/13

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Chang, H., & Tang, H. (2013). Feasibility analysis of the fixed-width pulse RZ feedback to reduce clock jitter effects in lowpass continuous-time ΔΣ modulators. In 2013 IEEE 56th International Midwest Symposium on Circuits and Systems, MWSCAS 2013 (pp. 245-248). [6674631] https://doi.org/10.1109/MWSCAS.2013.6674631