## Abstract

This paper presents novel architectures for fast binary addition which can be implemented using multiplexers only. Binary addition is carried out using a fast redundant-to-binary converter. It is shown that appropriate encoding of the redundant digits and recasting the binary addition as a redundant-to-binary conversion reduces the latency of addition from Wt_{fa} to Wt_{mux} where t_{fa} and t_{mux} respectively, represent binary full adder and multiplexer delays, and W is the word-length. A family of fast converter architectures is developed based on tree-type (obtained using look-ahead techniques) and carry-select approaches. The carry-generation component is the critical component in redundant-to-binary conversion and binary addition. It is shown that, if the word-length, W, is a power of two, then all carry signals can be generated in log_{2}Wt_{mux} time using W(log_{2}W-1)+1 multiplexers using a tree-type converter. It is shown that fastest binary addition can be performed using (Wlog_{2}W+1) multiplexers in time (log_{2}W+1)t_{mux}. If the specified converter latency is greater than log_{2}Wt_{mux}, then a family of converters using fewest multiplexers can be designed based on carry-select approach. It is shown that the power consumption in carry-select adders is minimized by increasing the number of segments in the adder.

Original language | English (US) |
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Title of host publication | IEEE Workshop on Signal Processing Systems, SiPS |

Subtitle of host publication | Design and Implementation |

Publisher | IEEE |

Pages | 232-241 |

Number of pages | 10 |

State | Published - Dec 1 1997 |

Event | Proceedings of the 1997 IEEE Workshop on Signal Processing Systems, SiPS 97: Design and Implementation - Leicester, UK Duration: Nov 3 1997 → Nov 5 1997 |

### Other

Other | Proceedings of the 1997 IEEE Workshop on Signal Processing Systems, SiPS 97: Design and Implementation |
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City | Leicester, UK |

Period | 11/3/97 → 11/5/97 |