Fast VLSI binary addition

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Scopus citations

Abstract

This paper presents novel architectures for fast binary addition which can be implemented using multiplexers only. Binary addition is carried out using a fast redundant-to-binary converter. It is shown that appropriate encoding of the redundant digits and recasting the binary addition as a redundant-to-binary conversion reduces the latency of addition from Wtfa to Wtmux where tfa and tmux respectively, represent binary full adder and multiplexer delays, and W is the word-length. A family of fast converter architectures is developed based on tree-type (obtained using look-ahead techniques) and carry-select approaches. The carry-generation component is the critical component in redundant-to-binary conversion and binary addition. It is shown that, if the word-length, W, is a power of two, then all carry signals can be generated in log2Wtmux time using W(log2W-1)+1 multiplexers using a tree-type converter. It is shown that fastest binary addition can be performed using (Wlog2W+1) multiplexers in time (log2W+1)tmux. If the specified converter latency is greater than log2Wtmux, then a family of converters using fewest multiplexers can be designed based on carry-select approach. It is shown that the power consumption in carry-select adders is minimized by increasing the number of segments in the adder.

Original languageEnglish (US)
Title of host publicationIEEE Workshop on Signal Processing Systems, SiPS
Subtitle of host publicationDesign and Implementation
PublisherIEEE
Pages232-241
Number of pages10
StatePublished - Dec 1 1997
EventProceedings of the 1997 IEEE Workshop on Signal Processing Systems, SiPS 97: Design and Implementation - Leicester, UK
Duration: Nov 3 1997Nov 5 1997

Other

OtherProceedings of the 1997 IEEE Workshop on Signal Processing Systems, SiPS 97: Design and Implementation
CityLeicester, UK
Period11/3/9711/5/97

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