Fast timing-driven partitioning-based placement for island style FPGAs

Pongstorn Maidee, Cristinel Ababei, Kia Bazargan

Research output: Contribution to journalConference articlepeer-review

51 Scopus citations


In this paper we propose a partitioning-based placement algorithm for FPGAs. The method incorporates simple, but effective heuristics that target delay minimization. The placement engine incorporates delay estimations obtained from previously placed and routed circuits using VPR [6]. As a result, the delay predictions during placement more accurately resemble those observed after detailed routing, which in turn leads to better delay optimization. An efficient terminal alignment heuristic for delay minimization is employed to further optimize the delay of the circuit in the routing phase. Simulation results show that the proposed technique can achieve comparable circuit delays (after routing) to those obtained with VPR while achieving a 7-fold speedup in placement runtime.

Original languageEnglish (US)
Pages (from-to)598-603
Number of pages6
JournalProceedings - Design Automation Conference
StatePublished - 2003
EventProceedings of the 40th Design Automation Conference - Anaheim, CA, United States
Duration: Jun 2 2003Jun 6 2003


  • FPGA placement
  • FPGAs
  • Partitioning based placement
  • Timing-driven placement


Dive into the research topics of 'Fast timing-driven partitioning-based placement for island style FPGAs'. Together they form a unique fingerprint.

Cite this