Fast tag comparator using diode partitioned domino for 64-bit microprocessors

Hrioaki Suzuki; Chris H. Kim; Kaushik Roy

doi:10.1109/TCSI.2006.885998

Fast tag comparator using diode partitioned domino for 64-bit microprocessors

Hrioaki Suzuki, Chris H. Kim, Kaushik Roy

Electrical and Computer Engineering

Research output: Contribution to journal › Article › peer-review

36 Scopus citations

Abstract

As the clock frequency and physical address space of 64-bit microprocessors continue to grow, one major critical path is the access to the on-die cache memory that includes a tag comparator, a tag SRAM and a data SRAM. To improve the delay of the tag comparator, a diode-partitioned (DP) domino circuit is proposed. DP domino reduces the parasitic capacitance and enables a smaller keeper in high fan-in gates. The diode circuit is also improved by an enhanced diode that boosts up the gate voltage of the nMOS diode. Delay of a 40-bit tag comparator using the proposed scheme is 33% faster than an optimized complex domino circuit in 1.8-V 180-nm CMOS technology.

Original language	English (US)
Pages (from-to)	322-328
Number of pages	7
Journal	IEEE Transactions on Circuits and Systems I: Regular Papers
Volume	54
Issue number	2
DOIs	https://doi.org/10.1109/TCSI.2006.885998
State	Published - Feb 2007

Bibliographical note

Funding Information:
Manuscript received October 6, 2004; revised December 7, 2005, and July 28, 2006. This work was supported in part by Semiconductor Research Corporation under Contract 1078.001. This paper was recommended by Associate Editor M. Stan.

Keywords

High-speed cache memory
High-speed domino circuit
Keeper design
Tag Comparator

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10.1109/TCSI.2006.885998

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@article{8fc02f7e93bc46209a9d4ef2eb02f224,

title = "Fast tag comparator using diode partitioned domino for 64-bit microprocessors",

abstract = "As the clock frequency and physical address space of 64-bit microprocessors continue to grow, one major critical path is the access to the on-die cache memory that includes a tag comparator, a tag SRAM and a data SRAM. To improve the delay of the tag comparator, a diode-partitioned (DP) domino circuit is proposed. DP domino reduces the parasitic capacitance and enables a smaller keeper in high fan-in gates. The diode circuit is also improved by an enhanced diode that boosts up the gate voltage of the nMOS diode. Delay of a 40-bit tag comparator using the proposed scheme is 33% faster than an optimized complex domino circuit in 1.8-V 180-nm CMOS technology.",

keywords = "High-speed cache memory, High-speed domino circuit, Keeper design, Tag Comparator",

author = "Hrioaki Suzuki and Kim, {Chris H.} and Kaushik Roy",

note = "Funding Information: Manuscript received October 6, 2004; revised December 7, 2005, and July 28, 2006. This work was supported in part by Semiconductor Research Corporation under Contract 1078.001. This paper was recommended by Associate Editor M. Stan.",

year = "2007",

month = feb,

doi = "10.1109/TCSI.2006.885998",

language = "English (US)",

volume = "54",

pages = "322--328",

journal = "IEEE Transactions on Circuits and Systems I: Regular Papers",

issn = "1057-7122",

number = "2",

}

TY - JOUR

T1 - Fast tag comparator using diode partitioned domino for 64-bit microprocessors

AU - Suzuki, Hrioaki

AU - Kim, Chris H.

AU - Roy, Kaushik

N1 - Funding Information: Manuscript received October 6, 2004; revised December 7, 2005, and July 28, 2006. This work was supported in part by Semiconductor Research Corporation under Contract 1078.001. This paper was recommended by Associate Editor M. Stan.

PY - 2007/2

Y1 - 2007/2

N2 - As the clock frequency and physical address space of 64-bit microprocessors continue to grow, one major critical path is the access to the on-die cache memory that includes a tag comparator, a tag SRAM and a data SRAM. To improve the delay of the tag comparator, a diode-partitioned (DP) domino circuit is proposed. DP domino reduces the parasitic capacitance and enables a smaller keeper in high fan-in gates. The diode circuit is also improved by an enhanced diode that boosts up the gate voltage of the nMOS diode. Delay of a 40-bit tag comparator using the proposed scheme is 33% faster than an optimized complex domino circuit in 1.8-V 180-nm CMOS technology.

AB - As the clock frequency and physical address space of 64-bit microprocessors continue to grow, one major critical path is the access to the on-die cache memory that includes a tag comparator, a tag SRAM and a data SRAM. To improve the delay of the tag comparator, a diode-partitioned (DP) domino circuit is proposed. DP domino reduces the parasitic capacitance and enables a smaller keeper in high fan-in gates. The diode circuit is also improved by an enhanced diode that boosts up the gate voltage of the nMOS diode. Delay of a 40-bit tag comparator using the proposed scheme is 33% faster than an optimized complex domino circuit in 1.8-V 180-nm CMOS technology.

KW - High-speed cache memory

KW - High-speed domino circuit

KW - Keeper design

KW - Tag Comparator

UR - http://www.scopus.com/inward/record.url?scp=33947381036&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=33947381036&partnerID=8YFLogxK

U2 - 10.1109/TCSI.2006.885998

DO - 10.1109/TCSI.2006.885998

M3 - Article

AN - SCOPUS:33947381036

SN - 1057-7122

VL - 54

SP - 322

EP - 328

JO - IEEE Transactions on Circuits and Systems I: Regular Papers

JF - IEEE Transactions on Circuits and Systems I: Regular Papers

IS - 2

ER -

Fast tag comparator using diode partitioned domino for 64-bit microprocessors

Abstract

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