Fast tag comparator using diode partitioned domino for 64-bit microprocessors

Hrioaki Suzuki, Chris H. Kim, Kaushik Roy

Research output: Contribution to journalArticlepeer-review

29 Scopus citations

Abstract

As the clock frequency and physical address space of 64-bit microprocessors continue to grow, one major critical path is the access to the on-die cache memory that includes a tag comparator, a tag SRAM and a data SRAM. To improve the delay of the tag comparator, a diode-partitioned (DP) domino circuit is proposed. DP domino reduces the parasitic capacitance and enables a smaller keeper in high fan-in gates. The diode circuit is also improved by an enhanced diode that boosts up the gate voltage of the nMOS diode. Delay of a 40-bit tag comparator using the proposed scheme is 33% faster than an optimized complex domino circuit in 1.8-V 180-nm CMOS technology.

Original languageEnglish (US)
Pages (from-to)322-328
Number of pages7
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Volume54
Issue number2
DOIs
StatePublished - Feb 2007

Bibliographical note

Funding Information:
Manuscript received October 6, 2004; revised December 7, 2005, and July 28, 2006. This work was supported in part by Semiconductor Research Corporation under Contract 1078.001. This paper was recommended by Associate Editor M. Stan.

Keywords

  • High-speed cache memory
  • High-speed domino circuit
  • Keeper design
  • Tag Comparator

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