As the clock frequency and physical address space of 64-bit microprocessors continue to grow, one major critical path is the access to the on-die cache memory that includes a tag comparator, a tag SRAM and a data SRAM. To improve the delay of the tag comparator, a diode-partitioned (DP) domino circuit is proposed. DP domino reduces the parasitic capacitance and enables a smaller keeper in high fan-in gates. The diode circuit is also improved by an enhanced diode that boosts up the gate voltage of the nMOS diode. Delay of a 40-bit tag comparator using the proposed scheme is 33% faster than an optimized complex domino circuit in 1.8-V 180-nm CMOS technology.
|Original language||English (US)|
|Number of pages||7|
|Journal||IEEE Transactions on Circuits and Systems I: Regular Papers|
|State||Published - Feb 2007|
Bibliographical noteFunding Information:
Manuscript received October 6, 2004; revised December 7, 2005, and July 28, 2006. This work was supported in part by Semiconductor Research Corporation under Contract 1078.001. This paper was recommended by Associate Editor M. Stan.
- High-speed cache memory
- High-speed domino circuit
- Keeper design
- Tag Comparator