Fast switch-level fault simulation using functional fault modeling

E. Vandris, G. Sobelman

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

A novel switch-level fault simulation method is presented for MOS circuits that combines compiled switch-level simulation techniques with functional fault modeling. The simulator models both node stuck-at-zero, stuck-at-one faults and transistor stuck-on, stuck-open faults. During compilation the switch-level circuit components are compiled into functional models. The effect of transistor faults on the function of the circuit components is modeled by functional fault models that execute very fast during simulation. The differential fault simulation algorithm developed for gate-level circuits is adapted for use at the switch-level and is shown to perform well, although it incurs a higher overhead due to the dynamic memory properties of MOS circuits.

Original languageEnglish (US)
Title of host publication1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers
PublisherPubl by IEEE
Pages74-77
Number of pages4
ISBN (Print)0818620552
StatePublished - Dec 1 1990
Event1990 IEEE International Conference on Computer-Aided Design - ICCAD-90 - Santa Clara, CA, USA
Duration: Nov 11 1990Nov 15 1990

Publication series

Name1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers

Other

Other1990 IEEE International Conference on Computer-Aided Design - ICCAD-90
CitySanta Clara, CA, USA
Period11/11/9011/15/90

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