Fast on-chip inductance simulation using a precorrected-FFT method

Haitian Hu, David T. Blaauw, Vladimir Zolotov, Kaushik Gala, Min Zhao, Rajendran Panda, Sachin S. Sapatnekar

Research output: Contribution to journalArticlepeer-review

11 Scopus citations

Abstract

In this paper, a precorrected-fast-Fourier-transform (FFT) approach for fast and highly accurate simulation of circuits with on-chip inductance is proposed. This work is motivated by the fact that circuit analysis and optimization methods based on the partial element equivalent circuit model require the solution of a subproblem in which a dense inductance matrix must be multiplied by a given vector, an operation with a high computational cost. Unlike traditional inductance extraction approaches, the precorrected-FFT method does not attempt to compute the inductance matrix explicitly, but assumes the entries in the given vector to be the fictitious currents in inductors and enables the accurate and quick computation of this matrix-vector product by exploiting the properties of the inductance calculation procedure. The effects of all of the inductors are implicitly considered in the calculation: faraway inductor effects are captured by representing the conductor currents as point currents on a grid, while nearby inductive interactions are modeled through direct calculation. The grid representation enables the use of the discrete FFT for fast magnetic vector potential calculation. The precorrected-FFT method has been applied to accurately simulate large industrial circuits with up to 121000 inductors and over 7 billion mutual inductive couplings in about 20 min. Techniques for trading off CPU time with accuracy using different approximation orders and grid constructions are also illustrated. Comparisons with a block-diagonal sparsification method are used to illustrate the accuracy and effectiveness of this method. In terms of accuracy, memory, and speed, it is shown that the precorrected-FFT method is an excellent approach for simulating on-chip inductance in a large circuit.

Original languageEnglish (US)
Pages (from-to)49-66
Number of pages18
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Volume22
Issue number1
DOIs
StatePublished - Jan 2003

Bibliographical note

Funding Information:
Manuscript received December 26, 2001; revised May 14, 2002. This paper was recommended by Associate Editor C.-J. Shi. This work was supported in part by the Science Research Council under Contract 99-TJ-714 and in part by the National Science Foundation under Award CCR-0098117.

Keywords

  • Circuit simulation
  • Electrostatic analysis
  • Inductance
  • Interconnect
  • Magnetic interaction
  • Model order reduction

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