Fast Mapping-Based High-Level Synthesis of Pipelined Circuits

Chaofan Li, Sachin S. Sapatnekar, Jiang Hu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

High level synthesis (HLS) is often employed as a frequently called kernel in design space exploration (DSE). Therefore, its nontrivial runtime becomes a bottleneck that prevents extensive solution search in DSE. In this work, we develop a mapping-based HLS technique that is fast and friendly to local incremental changes. It exploits the static-single assignment (SSA)-form intermediate representation (IR), starts with direct mapping from the IR to a fully pipelined circuit and performs incremental resource sharing in an iterative manner, which then alters the fully pipelined circuit to a partially pipelined or nonpipelined circuit. An algorithm is also proposed for automatic synthesis of pipeline interlocks to avoid structural hazards incurred by resource conflicts. Experimental results show that the proposed method is fast without loss of circuit performance in terms of throughput.

Original languageEnglish (US)
Title of host publicationProceedings of the 20th International Symposium on Quality Electronic Design, ISQED 2019
PublisherIEEE Computer Society
Pages33-38
Number of pages6
ISBN (Electronic)9781728103921
DOIs
StatePublished - Apr 23 2019
Event20th International Symposium on Quality Electronic Design, ISQED 2019 - Santa Clara, United States
Duration: Mar 6 2019Mar 7 2019

Publication series

NameProceedings - International Symposium on Quality Electronic Design, ISQED
Volume2019-March
ISSN (Print)1948-3287
ISSN (Electronic)1948-3295

Conference

Conference20th International Symposium on Quality Electronic Design, ISQED 2019
CountryUnited States
CitySanta Clara
Period3/6/193/7/19

Bibliographical note

Funding Information:
work is partially supported by NSF (CCF-1525749,CCF-1525925).

Funding Information:
This work is partially supported by NSF (CCF-1525749,CCF-1525925).

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