Abstract
This work addresses a fast low-power implementation of a shared division and square-root architecture. Two approaches are considered: the Sweeney, Robertson and Tocher (SRT) approach and the generalized Svoboda and Tung (GST) approach. Two contributions will be made. First, a GST square-root architecture is developed without requiring an additional division by the scaling factor after the square-root operation. Second, a quantitative comparison of speed and power consumption of GST and SRT division/square-root units is carried out.
| Original language | English (US) |
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| Pages | 128-135 |
| Number of pages | 8 |
| State | Published - Dec 1 1998 |
| Event | Proceedings of the 1998 IEEE International Conference on Computer Design - Austin, TX, USA Duration: Oct 5 1998 → Oct 7 1998 |
Other
| Other | Proceedings of the 1998 IEEE International Conference on Computer Design |
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| City | Austin, TX, USA |
| Period | 10/5/98 → 10/7/98 |