Fast low-energy VLSI binary addition

Research output: Chapter in Book/Report/Conference proceedingConference contribution

16 Scopus citations

Abstract

This paper presents novel architectures for fast binary addition which can be implemented using multiplexers only. Binary addition is carried out using a fast redundant-to-binary converter. It is shown that appropriate encoding of the redundant digits and recasting the binary addition as a redundant-to-binary conversion reduces the latency of addition from Wtfa to Wtmux where tfa and tmux, respectively, represent binary full adder and multiplexer delays, and W is the word-length. A family of fast converter architectures is developed based on tree-type (obtained using look-ahead techniques) and carry-select approaches. The carry-generation component is the critical component in redundant-to-binary conversion and binary addition. It is shown that fastest binary addition can be performed using (Wlog2W+W+1) multiplexers in time (log2W+2)tmux. If the specified adder latency is greater than (log2W+2)tmux, then a family of converters using fewest multiplexers can be designed based on carry-select approach. Finally a class of hybrid adders are designed by using a carry-select configuration and by substituting tree-based blocks in place of some carry-select blocks. It is shown that this approach can lead to adder designs which consume the least energy.

Original languageEnglish (US)
Title of host publicationProceedings - IEEE International Conference on Computer Design
Subtitle of host publicationVLSI in Computers and Processors
Editors Anon
PublisherIEEE
Pages676-684
Number of pages9
StatePublished - Dec 1 1997
EventProceedings of the 1997 International Conference on Computer Design - Austin, TX, USA
Duration: Oct 12 1997Oct 15 1997

Other

OtherProceedings of the 1997 International Conference on Computer Design
CityAustin, TX, USA
Period10/12/9710/15/97

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