Fast low-energy VLSI binary addition

This paper presents novel architectures for fast binary addition which can be implemented using multiplexers only. Binary addition is carried out using a fast redundant-to-binary converter. It is shown that appropriate encoding of the redundant digits and recasting the binary addition as a redundant-to-binary conversion reduces the latency of addition from Wt_fa to Wt_mux where t_fa and t_mux, respectively, represent binary full adder and multiplexer delays, and W is the word-length. A family of fast converter architectures is developed based on tree-type (obtained using look-ahead techniques) and carry-select approaches. The carry-generation component is the critical component in redundant-to-binary conversion and binary addition. It is shown that fastest binary addition can be performed using (Wlog₂W+W+1) multiplexers in time (log₂W+2)t_mux. If the specified adder latency is greater than (log₂W+2)t_mux, then a family of converters using fewest multiplexers can be designed based on carry-select approach. Finally a class of hybrid adders are designed by using a carry-select configuration and by substituting tree-based blocks in place of some carry-select blocks. It is shown that this approach can lead to adder designs which consume the least energy.