Fast hierarchical floorplanning with congestion and timing control

A. Ranjan, K. Bazargan, M. Sarrafzadeh

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Scopus citations

Abstract

We propose fresher looks into already existing hierarchical partitioning based floorplan design methods and their relevance in providing faster alternatives to conventional approaches. We modify the existing partitioning based floor-planner to handle congestion and timing. We also explore the applicability of traditional Sizing Theorem for combining two modules based on their sizes and interconnecting wirelength. The results show that our floorplanning approach can produce floorplans hundred times faster and at the same time achieving better quality (on average 20% better wirelength, better congestion and better timing optimization) than that of pure Simulated Annealing based floorplanner.

Original languageEnglish (US)
Title of host publicationProceedings - IEEE International Conference on Computer Design
Subtitle of host publicationVLSI in Computers and Processors
PublisherIEEE
Pages357-362
Number of pages6
StatePublished - Jan 1 2000
Event2000 International Conference on Computer Design - Austin, TX, USA
Duration: Sep 17 2000Sep 20 2000

Other

Other2000 International Conference on Computer Design
CityAustin, TX, USA
Period9/17/009/20/00

Fingerprint Dive into the research topics of 'Fast hierarchical floorplanning with congestion and timing control'. Together they form a unique fingerprint.

Cite this