Fast estimation of area-delay trade-offs in circuit sizing

Shrirang K. Karandikar; Sachin S. Sapatnekar

doi:10.1109/ISCAS.2005.1465402

Fast estimation of area-delay trade-offs in circuit sizing

Shrirang K. Karandikar
, Sachin S. Sapatnekar

Electrical and Computer Engineering

Research output: Contribution to journal › Conference article › peer-review

4 Scopus citations

Abstract

Appropriately sizing a circuit can improve its performance signicantly. However, this is a time consuming transform, and it is therefore difcult to compare different implementations of a circuit in terms of the cost overhead required for a particular delay target. This paper presents a fast estimator of the complete area-delay trade-off curve of a given circuit, allowing a designer to choose the most appropriate implementation for a given delay. We observe excellent delity with the actual area-delay curves (94.13% correct comparisons), with an average error of 5.76% in the area differences predicted.

Original language	English (US)
Article number	1465402
Pages (from-to)	3575-3578
Number of pages	4
Journal	Proceedings - IEEE International Symposium on Circuits and Systems
DOIs	https://doi.org/10.1109/ISCAS.2005.1465402
State	Published - 2005
Event	IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005 - Kobe, Japan Duration: May 23 2005 → May 26 2005

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10.1109/ISCAS.2005.1465402

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title = "Fast estimation of area-delay trade-offs in circuit sizing",

abstract = "Appropriately sizing a circuit can improve its performance signicantly. However, this is a time consuming transform, and it is therefore difcult to compare different implementations of a circuit in terms of the cost overhead required for a particular delay target. This paper presents a fast estimator of the complete area-delay trade-off curve of a given circuit, allowing a designer to choose the most appropriate implementation for a given delay. We observe excellent delity with the actual area-delay curves (94.13\% correct comparisons), with an average error of 5.76\% in the area differences predicted.",

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journal = "Proceedings - IEEE International Symposium on Circuits and Systems",

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AU - Sapatnekar, Sachin S.

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N2 - Appropriately sizing a circuit can improve its performance signicantly. However, this is a time consuming transform, and it is therefore difcult to compare different implementations of a circuit in terms of the cost overhead required for a particular delay target. This paper presents a fast estimator of the complete area-delay trade-off curve of a given circuit, allowing a designer to choose the most appropriate implementation for a given delay. We observe excellent delity with the actual area-delay curves (94.13% correct comparisons), with an average error of 5.76% in the area differences predicted.

AB - Appropriately sizing a circuit can improve its performance signicantly. However, this is a time consuming transform, and it is therefore difcult to compare different implementations of a circuit in terms of the cost overhead required for a particular delay target. This paper presents a fast estimator of the complete area-delay trade-off curve of a given circuit, allowing a designer to choose the most appropriate implementation for a given delay. We observe excellent delity with the actual area-delay curves (94.13% correct comparisons), with an average error of 5.76% in the area differences predicted.

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EP - 3578

JO - Proceedings - IEEE International Symposium on Circuits and Systems

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M1 - 1465402

T2 - IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005

Y2 - 23 May 2005 through 26 May 2005

ER -

Fast estimation of area-delay trade-offs in circuit sizing

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