Fast disjoint transistor networks from BDDs

Leomar S. Da Rosa, Felipe S. Marques, Tiago M.G. Cardoso, Renato P. Ribas, Sachin S. Sapatnekar, André I. Reis

Research output: Chapter in Book/Report/Conference proceedingConference contribution

10 Scopus citations

Abstract

In this paper, we describe different ways to derive transistor networks from BDDs. The use of disjoint pull-up (composed of PMOS transistors) and pull-down (composed of NMOS transistors) planes allows simplifications that result in shorter pull-up and pull-down transistor stacks. The reduced length of transistor stacks leads to the fastest implementation among the six different strategies evaluated to generate transistor networks from BDDs. Delay and area results are presented showing the impact of the proposed strategy.

Original languageEnglish (US)
Title of host publicationProceedings SBCCI 2006 - 19th Symposium on Integrated Circuits and Systems Design
Pages137-142
Number of pages6
StatePublished - Nov 16 2006
EventSBCCI 2006 - 19th Symposium on Integrated Circuits and Systems Design - Minas Gerais, Brazil
Duration: Aug 28 2006Sep 1 2006

Publication series

NameSBCCI 2006 - 19th Symposium on Integrated Circuits and Systems Design
Volume2006

Other

OtherSBCCI 2006 - 19th Symposium on Integrated Circuits and Systems Design
CountryBrazil
CityMinas Gerais
Period8/28/069/1/06

Keywords

  • BDDs
  • CMOS gates
  • PTL
  • Switch theory
  • Unateness

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