### Abstract

Net extraction is crucial in VLSI design verification. Current algorithms for net extraction do not exploit the fact that the number, c, of different orientations of the line segments or polygon edges in a practical VLSI mask design is small relative to the number, n, of segments or edges. Instead they rely on computing all intersections in the input and hence take time that is at least proportional to the number of intersections. In this paper we develop a simple and practical algorithm for net extraction that runs in O(cn log n) time and O(n) space, which is optimal for fixed c. Experiments indicate that the algorithm will generally outperform existing algorithms on practical VLSI designs. We expect that the techniques presented will be useful in other VLSI/CAD problems that operate with restricted orientation geometries.

Original language | English (US) |
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Title of host publication | Proc 1993 IEEE ACM Int Conf Comput Aided Des |

Editors | Anon |

Publisher | Publ by IEEE |

Pages | 770-774 |

Number of pages | 5 |

ISBN (Print) | 0818644923 |

State | Published - Dec 1 1993 |

Event | Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design - Santa Clara, CA, USA Duration: Nov 7 1993 → Nov 11 1993 |

### Other

Other | Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design |
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City | Santa Clara, CA, USA |

Period | 11/7/93 → 11/11/93 |

### Fingerprint

### Cite this

*Proc 1993 IEEE ACM Int Conf Comput Aided Des*(pp. 770-774). Publ by IEEE.

**Fast algorithm for VLSI net extraction.** / Lopez, Mario A.; Janardan, Ravi; Sahni, Sartaj.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

*Proc 1993 IEEE ACM Int Conf Comput Aided Des.*Publ by IEEE, pp. 770-774, Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, Santa Clara, CA, USA, 11/7/93.

}

TY - GEN

T1 - Fast algorithm for VLSI net extraction

AU - Lopez, Mario A.

AU - Janardan, Ravi

AU - Sahni, Sartaj

PY - 1993/12/1

Y1 - 1993/12/1

N2 - Net extraction is crucial in VLSI design verification. Current algorithms for net extraction do not exploit the fact that the number, c, of different orientations of the line segments or polygon edges in a practical VLSI mask design is small relative to the number, n, of segments or edges. Instead they rely on computing all intersections in the input and hence take time that is at least proportional to the number of intersections. In this paper we develop a simple and practical algorithm for net extraction that runs in O(cn log n) time and O(n) space, which is optimal for fixed c. Experiments indicate that the algorithm will generally outperform existing algorithms on practical VLSI designs. We expect that the techniques presented will be useful in other VLSI/CAD problems that operate with restricted orientation geometries.

AB - Net extraction is crucial in VLSI design verification. Current algorithms for net extraction do not exploit the fact that the number, c, of different orientations of the line segments or polygon edges in a practical VLSI mask design is small relative to the number, n, of segments or edges. Instead they rely on computing all intersections in the input and hence take time that is at least proportional to the number of intersections. In this paper we develop a simple and practical algorithm for net extraction that runs in O(cn log n) time and O(n) space, which is optimal for fixed c. Experiments indicate that the algorithm will generally outperform existing algorithms on practical VLSI designs. We expect that the techniques presented will be useful in other VLSI/CAD problems that operate with restricted orientation geometries.

UR - http://www.scopus.com/inward/record.url?scp=0027839132&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0027839132&partnerID=8YFLogxK

M3 - Conference contribution

SN - 0818644923

SP - 770

EP - 774

BT - Proc 1993 IEEE ACM Int Conf Comput Aided Des

A2 - Anon, null

PB - Publ by IEEE

ER -