Fast algorithm for VLSI net extraction

Mario A. Lopez, Ravi Janardan, Sartaj Sahni

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

Net extraction is crucial in VLSI design verification. Current algorithms for net extraction do not exploit the fact that the number, c, of different orientations of the line segments or polygon edges in a practical VLSI mask design is small relative to the number, n, of segments or edges. Instead they rely on computing all intersections in the input and hence take time that is at least proportional to the number of intersections. In this paper we develop a simple and practical algorithm for net extraction that runs in O(cn log n) time and O(n) space, which is optimal for fixed c. Experiments indicate that the algorithm will generally outperform existing algorithms on practical VLSI designs. We expect that the techniques presented will be useful in other VLSI/CAD problems that operate with restricted orientation geometries.

Original languageEnglish (US)
Title of host publicationProc 1993 IEEE ACM Int Conf Comput Aided Des
Editors Anon
PublisherPubl by IEEE
Pages770-774
Number of pages5
ISBN (Print)0818644923
StatePublished - Dec 1 1993
EventProceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design - Santa Clara, CA, USA
Duration: Nov 7 1993Nov 11 1993

Publication series

NameProc 1993 IEEE ACM Int Conf Comput Aided Des

Other

OtherProceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design
CitySanta Clara, CA, USA
Period11/7/9311/11/93

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