Failure analysis of asymmetric aging under NBTI

With CMOS technology scaling, design for reliability has become an important step in the design cycle and increased the need for efficient and accurate aging simulation methods during the design stage. NBTI-induced delay shifts in logic paths are asymmetric in nature, as opposed to the averaging effect due to recovery assumed in traditional aging analysis. Timing violations due to aging, in particular, are very sensitive to the standby operation regime of a digital circuit. In this paper, by identifying the critical moments in circuit operation and considering the asymmetric aging effects, timing violations under NBTI effect are correctly predicted. The unique contributions of this work include the following: 1) Accurate modeling of aging-induced gate delay shift due to transistor threshold voltage (V^th) shift, using only the delay dependence on supply voltage from cell library, is presented; 2) an efficient simulation flow for asymmetric aging analysis is proposed and conducted at critical points in circuit operation; and 3) timing violations due to NBTI aging are investigated in sequential circuits and the proposed framework is tested in VLSI applications such as DDR memory and SRAM caches. This methodology is comprehensively demonstrated with ISCAS89 benchmark circuits using a 45-nm Nangate standard cell library characterized using predictive technology models. Our proposed failure assessment provides design insights and enables resilient techniques for mitigating digital circuit aging.