Exploring sub-block value reuse for superscalar processors

Jian Huang, David J. Lilja

Research output: Contribution to journalConference articlepeer-review

13 Scopus citations


The performance potential of a value reuse mechanism depends on its reuse detection time, the number of reuse opportunities, and the amount of work saved by skipping each reuse unit. Since larger instruction groups typically have fewer reuse opportunities than smaller groups, but also provide greater benefit for each reuse-detection process, it is very important to find the balance point that provides the largest overall performance gain. We propose a new mechanism called sub-block reuse to balance the reuse granularity and the number of reuse opportunities. Our simulation results show that sub-block reuse with compiler assistance has a substantial and consistent potential to improve the performance of superscalar processors, with speedups ranging from 10% to 22%.

Original languageEnglish (US)
Pages (from-to)100-107
Number of pages8
JournalParallel Architectures and Compilation Techniques - Conference Proceedings, PACT
StatePublished - 2000
Event2000 International Conference on Parallel Architectures and Compilation Techniques - Philadelphia, PA, USA
Duration: Oct 15 2000Oct 19 2000


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