Exploring speculative parallelism in SPEC2006

Venkatesan Packirisamy, Antonia Zhai, Wei Chung Hsu, Pen Chung Yew, Tin Fook Ngai

Research output: Chapter in Book/Report/Conference proceedingConference contribution

33 Scopus citations

Abstract

The computer industry has adopted multi-threaded and multicore architectures as the clock rate increase stalled in early 2000's. It was hoped that the continuous improvement of single-program performance could be achieved through these architectures. However, traditional parallelizing compilers often fail to effectively parallelize general-purpose applications which typically have complex control flow and excessive pointer usage. Recently hardware techniques such as Transactional Memory (TM) and Thread- Level Speculation (TLS) have been proposed to simplify the task of parallelization by using speculative threads. Potential of speculative parallelism in general-purpose applications like SPEC CPU 2000 have been well studied and shown to be moderately successful. Preliminary work examining the potential parallelism in SPEC2006 deployed parallel threads with a restrictive TLS execution model and limited compiler support, and thus only showed limited performance potential. In this paper, we first analyze the cross-iteration dependence behavior of SPEC 2006 benchmarks and show that more parallelism potential is available in SPEC 2006 benchmarks, comparing to SPEC2000. We further use a state-of-the-art profile-driven TLS compiler to identify loops that can be speculatively parallelized. Overall, we found that with optimal loop selection we can potentially achieve an average speedup of 60% on four cores over what could be achieved by a traditional parallelizing compiler such as Intel's ICC compiler.We also found that an additional 11% improvement can be potentially obtained on selected benchmarks using 8 cores when we extend TLS on multiple loop levels as opposed to restricting to a single loop level.

Original languageEnglish (US)
Title of host publicationISPASS 2009 - International Symposium on Performance Analysis of Systems and Software
Pages77-88
Number of pages12
DOIs
StatePublished - 2009
EventInternational Symposium on Performance Analysis of Systems and Software, ISPASS 2009 - Boston, MA, United States
Duration: Apr 26 2009Apr 28 2009

Publication series

NameISPASS 2009 - International Symposium on Performance Analysis of Systems and Software

Other

OtherInternational Symposium on Performance Analysis of Systems and Software, ISPASS 2009
Country/TerritoryUnited States
CityBoston, MA
Period4/26/094/28/09

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