Abstract
A new timing-driven partitioning-based placement tool for 3D FPGA integration is presented. The circuit is first divided into layers with limited number of inter-layer vias, and then placement is performed on individual layers, while minimizing the delay of critical paths. We use our tool as a platform for exploring potential benefits in terms of delay and wire-length that 3D technologies can offer for FPGA fabrics. We show that 3D integration results in wire-length reduction for FPGA designs. Our empirical analysis shows that wire-length can be reduced by up to 50% using ten layers. Delay reductions are estimated to be more than 30% if multi-segment lengths are employed between layers.
| Original language | English (US) |
|---|---|
| Title of host publication | Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) |
| Editors | Jurgen Becker, Marco Platzner, Serge Vernalde |
| Publisher | Springer Verlag |
| Pages | 874-880 |
| Number of pages | 7 |
| ISBN (Print) | 3540229892, 9783540229896 |
| DOIs | |
| State | Published - 2004 |
| Event | 14th International Conference on Field Programmable Logic and Applications, FPL 2004 - Antwerp, Belgium Duration: Aug 30 2004 → Sep 1 2004 |
Publication series
| Name | Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) |
|---|---|
| Volume | 3203 |
| ISSN (Print) | 0302-9743 |
| ISSN (Electronic) | 1611-3349 |
Other
| Other | 14th International Conference on Field Programmable Logic and Applications, FPL 2004 |
|---|---|
| Country/Territory | Belgium |
| City | Antwerp |
| Period | 8/30/04 → 9/1/04 |
Bibliographical note
Publisher Copyright:© Springer-Verlag Berlin Heidelberg 2004.