Exploring potential benefits of 3D FPGA integration

Cristinel Ababei, Pongstorn Maidee, Kia Bazargan

Research output: Chapter in Book/Report/Conference proceedingConference contribution

32 Scopus citations

Abstract

A new timing-driven partitioning-based placement tool for 3D FPGA integration is presented. The circuit is first divided into layers with limited number of inter-layer vias, and then placement is performed on individual layers, while minimizing the delay of critical paths. We use our tool as a platform for exploring potential benefits in terms of delay and wire-length that 3D technologies can offer for FPGA fabrics. We show that 3D integration results in wire-length reduction for FPGA designs. Our empirical analysis shows that wire-length can be reduced by up to 50% using ten layers. Delay reductions are estimated to be more than 30% if multi-segment lengths are employed between layers.

Original languageEnglish (US)
Title of host publicationLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
EditorsJurgen Becker, Marco Platzner, Serge Vernalde
PublisherSpringer Verlag
Pages874-880
Number of pages7
ISBN (Print)3540229892, 9783540229896
DOIs
StatePublished - 2004
Event14th International Conference on Field Programmable Logic and Applications, FPL 2004 - Antwerp, Belgium
Duration: Aug 30 2004Sep 1 2004

Publication series

NameLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume3203
ISSN (Print)0302-9743
ISSN (Electronic)1611-3349

Other

Other14th International Conference on Field Programmable Logic and Applications, FPL 2004
CountryBelgium
CityAntwerp
Period8/30/049/1/04

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