Exploring fine-grained fault tolerance for nanotechnology devices with the recursive nanobox processor grid

A. J. Kleinosowski, Vasudev V. Pai, Vijay Rangarajan, Priyadarshini Ranganath, Kevin Kleinosowski, Mahesh Subramony, David J. Lilja

Research output: Contribution to journalArticlepeer-review

10 Scopus citations

Abstract

Advanced molecular nanotechnology devices are predicted to have exceedingly high transient fault rates and large numbers of inherent device defects compared to conventional CMOS devices. We describe and evaluate the Recursive NanoBox Processor Grid as an application specific, fault-tolerant, parallel computing system designed for fabrication with unreliable nanotechnology devices. In this study we construct hardware description language models of a NanoBox Processor cell and evaluate the effectiveness of our recursive fault masking approach in the presence of random errors. Our analysis shows that complex circuits constructed with encoded lookup tables can operate correctly despite 2% of the nodes being in error. The circuits operate partially correct with up to 4% of the nodes being in error.

Original languageEnglish (US)
Article number1695958
Pages (from-to)575-586
Number of pages12
JournalIEEE Transactions on Nanotechnology
Volume5
Issue number5
DOIs
StatePublished - Sep 2006

Bibliographical note

Funding Information:
Manuscript received April 17, 2006; revised May 1, 2006. This work was supported in part by IBM, Intel, and Semiconductor Research Corporation under Contract2004-HJ-1190, in part by the National Science Foundation (NSF) under Grant CCR-0210197, in part by the University of Minnesota Digital Technology Center, and in part by the Minnesota Supercomputing Institute. The review of this paper was arranged by Associate Editor W. Porod.

Copyright:
Copyright 2008 Elsevier B.V., All rights reserved.

Keywords

  • Computer architecture
  • Fault tolerance
  • Logic design
  • Nanotechnology
  • Robustness

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