Exploring a machine learning approach to performance driven analog IC placement

Yaguang Li, Yishuang Lin, Meghna Madhusudan, Arvind Sharma, Wenbin Xu, Sachin Sapatnekar, Ramesh Harjani, Jiang Hu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Scopus citations

Abstract

Analog IC layout is usually a time-consuming manual design process. Although automated analog IC layout has been studied for decades, most of the previous works are focused on geometric constraints. As a result, there is often a performance gap compared to manual designs, which prevents the automated tools from wide applications. The recent progress on machine learning technology offers an opportunity for solving this problem. In this work, several machine learning techniques are investigated for analog IC performance prediction, which is further applied for performance driven placement. Simulation results from several amplifier designs indicate that the proposed approach can achieve performance similar to manual layout but is orders of magnitude faster.

Original languageEnglish (US)
Title of host publicationProceedings - 2020 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2020
PublisherIEEE Computer Society
Pages24-29
Number of pages6
ISBN (Electronic)9781728157757
DOIs
StatePublished - Jul 2020
Event19th IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2020 - Limassol, Cyprus
Duration: Jul 6 2020Jul 8 2020

Publication series

NameProceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI
Volume2020-July
ISSN (Print)2159-3469
ISSN (Electronic)2159-3477

Conference

Conference19th IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2020
CountryCyprus
CityLimassol
Period7/6/207/8/20

Bibliographical note

Funding Information:
ACKNOWLEDGEMENT This work is supported by the DARPA ERI IDEA program.

Keywords

  • Analog IC
  • Machine Learning
  • Placement

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