Analog IC layout is usually a time-consuming manual design process. Although automated analog IC layout has been studied for decades, most of the previous works are focused on geometric constraints. As a result, there is often a performance gap compared to manual designs, which prevents the automated tools from wide applications. The recent progress on machine learning technology offers an opportunity for solving this problem. In this work, several machine learning techniques are investigated for analog IC performance prediction, which is further applied for performance driven placement. Simulation results from several amplifier designs indicate that the proposed approach can achieve performance similar to manual layout but is orders of magnitude faster.
|Original language||English (US)|
|Title of host publication||Proceedings - 2020 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2020|
|Publisher||IEEE Computer Society|
|Number of pages||6|
|State||Published - Jul 2020|
|Event||19th IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2020 - Limassol, Cyprus|
Duration: Jul 6 2020 → Jul 8 2020
|Name||Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI|
|Conference||19th IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2020|
|Period||7/6/20 → 7/8/20|
Bibliographical noteFunding Information:
ACKNOWLEDGEMENT This work is supported by the DARPA ERI IDEA program.
© 2020 IEEE.
- Analog IC
- Machine Learning