Exploring a machine learning approach to performance driven analog IC placement

Yaguang Li; Yishuang Lin; Meghna Madhusudan; Arvind K Sharma; Wenbin Xu; Sachin Sapatnekar; Ramesh Harjani; Jiang Hu

doi:10.1109/ISVLSI49217.2020.00015

Exploring a machine learning approach to performance driven analog IC placement

Yaguang Li, Yishuang Lin, Meghna Madhusudan, Arvind K Sharma, Wenbin Xu, Sachin Sapatnekar, Ramesh Harjani, Jiang Hu

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

20 Scopus citations

Abstract

Analog IC layout is usually a time-consuming manual design process. Although automated analog IC layout has been studied for decades, most of the previous works are focused on geometric constraints. As a result, there is often a performance gap compared to manual designs, which prevents the automated tools from wide applications. The recent progress on machine learning technology offers an opportunity for solving this problem. In this work, several machine learning techniques are investigated for analog IC performance prediction, which is further applied for performance driven placement. Simulation results from several amplifier designs indicate that the proposed approach can achieve performance similar to manual layout but is orders of magnitude faster.

Original language	English (US)
Title of host publication	Proceedings - 2020 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2020
Publisher	IEEE Computer Society
Pages	24-29
Number of pages	6
ISBN (Electronic)	9781728157757
DOIs	https://doi.org/10.1109/ISVLSI49217.2020.00015
State	Published - Jul 2020
Event	19th IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2020 - Limassol, Cyprus Duration: Jul 6 2020 → Jul 8 2020

Publication series

Name	Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI
Volume	2020-July
ISSN (Print)	2159-3469
ISSN (Electronic)	2159-3477

Conference

Conference	19th IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2020
Country/Territory	Cyprus
City	Limassol
Period	7/6/20 → 7/8/20

Bibliographical note

Publisher Copyright:
© 2020 IEEE.

Keywords

Analog IC
Machine Learning
Placement

Publisher link

10.1109/ISVLSI49217.2020.00015

Find It

Find It at U of M Libraries

Cite this

Li, Y., Lin, Y., Madhusudan, M., Sharma, A. K., Xu, W., Sapatnekar, S., Harjani, R., & Hu, J. (2020). Exploring a machine learning approach to performance driven analog IC placement. In Proceedings - 2020 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2020 (pp. 24-29). Article 9154987 (Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI; Vol. 2020-July). IEEE Computer Society. https://doi.org/10.1109/ISVLSI49217.2020.00015

Exploring a machine learning approach to performance driven analog IC placement. / Li, Yaguang; Lin, Yishuang; Madhusudan, Meghna et al.
Proceedings - 2020 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2020. IEEE Computer Society, 2020. p. 24-29 9154987 (Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI; Vol. 2020-July).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Li, Y, Lin, Y, Madhusudan, M, Sharma, AK, Xu, W, Sapatnekar, S , Harjani, R & Hu, J 2020, Exploring a machine learning approach to performance driven analog IC placement. in Proceedings - 2020 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2020., 9154987, Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI, vol. 2020-July, IEEE Computer Society, pp. 24-29, 19th IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2020, Limassol, Cyprus, 7/6/20. https://doi.org/10.1109/ISVLSI49217.2020.00015

Li Y, Lin Y, Madhusudan M, Sharma AK, Xu W, Sapatnekar S et al. Exploring a machine learning approach to performance driven analog IC placement. In Proceedings - 2020 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2020. IEEE Computer Society. 2020. p. 24-29. 9154987. (Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI). doi: 10.1109/ISVLSI49217.2020.00015

@inproceedings{c0e941f93ab7472fafe839943b74cd1e,

title = "Exploring a machine learning approach to performance driven analog IC placement",

abstract = "Analog IC layout is usually a time-consuming manual design process. Although automated analog IC layout has been studied for decades, most of the previous works are focused on geometric constraints. As a result, there is often a performance gap compared to manual designs, which prevents the automated tools from wide applications. The recent progress on machine learning technology offers an opportunity for solving this problem. In this work, several machine learning techniques are investigated for analog IC performance prediction, which is further applied for performance driven placement. Simulation results from several amplifier designs indicate that the proposed approach can achieve performance similar to manual layout but is orders of magnitude faster.",

keywords = "Analog IC, Machine Learning, Placement",

author = "Yaguang Li and Yishuang Lin and Meghna Madhusudan and Sharma, {Arvind K} and Wenbin Xu and Sachin Sapatnekar and Ramesh Harjani and Jiang Hu",

note = "Publisher Copyright: {\textcopyright} 2020 IEEE.; 19th IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2020 ; Conference date: 06-07-2020 Through 08-07-2020",

year = "2020",

month = jul,

doi = "10.1109/ISVLSI49217.2020.00015",

language = "English (US)",

series = "Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI",

publisher = "IEEE Computer Society",

pages = "24--29",

booktitle = "Proceedings - 2020 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2020",

}

TY - GEN

T1 - Exploring a machine learning approach to performance driven analog IC placement

AU - Li, Yaguang

AU - Lin, Yishuang

AU - Madhusudan, Meghna

AU - Sharma, Arvind K

AU - Xu, Wenbin

AU - Sapatnekar, Sachin

AU - Harjani, Ramesh

AU - Hu, Jiang

PY - 2020/7

Y1 - 2020/7

N2 - Analog IC layout is usually a time-consuming manual design process. Although automated analog IC layout has been studied for decades, most of the previous works are focused on geometric constraints. As a result, there is often a performance gap compared to manual designs, which prevents the automated tools from wide applications. The recent progress on machine learning technology offers an opportunity for solving this problem. In this work, several machine learning techniques are investigated for analog IC performance prediction, which is further applied for performance driven placement. Simulation results from several amplifier designs indicate that the proposed approach can achieve performance similar to manual layout but is orders of magnitude faster.

AB - Analog IC layout is usually a time-consuming manual design process. Although automated analog IC layout has been studied for decades, most of the previous works are focused on geometric constraints. As a result, there is often a performance gap compared to manual designs, which prevents the automated tools from wide applications. The recent progress on machine learning technology offers an opportunity for solving this problem. In this work, several machine learning techniques are investigated for analog IC performance prediction, which is further applied for performance driven placement. Simulation results from several amplifier designs indicate that the proposed approach can achieve performance similar to manual layout but is orders of magnitude faster.

KW - Analog IC

KW - Machine Learning

KW - Placement

UR - http://www.scopus.com/inward/record.url?scp=85090419319&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85090419319&partnerID=8YFLogxK

U2 - 10.1109/ISVLSI49217.2020.00015

DO - 10.1109/ISVLSI49217.2020.00015

M3 - Conference contribution

AN - SCOPUS:85090419319

T3 - Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI

SP - 24

EP - 29

BT - Proceedings - 2020 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2020

PB - IEEE Computer Society

T2 - 19th IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2020

Y2 - 6 July 2020 through 8 July 2020

ER -

Exploring a machine learning approach to performance driven analog IC placement

Abstract

Publication series

Conference

Bibliographical note

Keywords

Publisher link

Find It

Other files and links

Fingerprint

Cite this